esp32s3/assist_debug/
core_0_montr_ena.rs

1#[doc = "Register `CORE_0_MONTR_ENA` reader"]
2pub type R = crate::R<CORE_0_MONTR_ENA_SPEC>;
3#[doc = "Register `CORE_0_MONTR_ENA` writer"]
4pub type W = crate::W<CORE_0_MONTR_ENA_SPEC>;
5#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_ENA` reader - Core0 dram0 area0 read monitor enable"]
6pub type CORE_0_AREA_DRAM0_0_RD_ENA_R = crate::BitReader;
7#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_ENA` writer - Core0 dram0 area0 read monitor enable"]
8pub type CORE_0_AREA_DRAM0_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_ENA` reader - Core0 dram0 area0 write monitor enable"]
10pub type CORE_0_AREA_DRAM0_0_WR_ENA_R = crate::BitReader;
11#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_ENA` writer - Core0 dram0 area0 write monitor enable"]
12pub type CORE_0_AREA_DRAM0_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_ENA` reader - Core0 dram0 area1 read monitor enable"]
14pub type CORE_0_AREA_DRAM0_1_RD_ENA_R = crate::BitReader;
15#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_ENA` writer - Core0 dram0 area1 read monitor enable"]
16pub type CORE_0_AREA_DRAM0_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_ENA` reader - Core0 dram0 area1 write monitor enable"]
18pub type CORE_0_AREA_DRAM0_1_WR_ENA_R = crate::BitReader;
19#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_ENA` writer - Core0 dram0 area1 write monitor enable"]
20pub type CORE_0_AREA_DRAM0_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CORE_0_AREA_PIF_0_RD_ENA` reader - Core0 PIF area0 read monitor enable"]
22pub type CORE_0_AREA_PIF_0_RD_ENA_R = crate::BitReader;
23#[doc = "Field `CORE_0_AREA_PIF_0_RD_ENA` writer - Core0 PIF area0 read monitor enable"]
24pub type CORE_0_AREA_PIF_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CORE_0_AREA_PIF_0_WR_ENA` reader - Core0 PIF area0 write monitor enable"]
26pub type CORE_0_AREA_PIF_0_WR_ENA_R = crate::BitReader;
27#[doc = "Field `CORE_0_AREA_PIF_0_WR_ENA` writer - Core0 PIF area0 write monitor enable"]
28pub type CORE_0_AREA_PIF_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CORE_0_AREA_PIF_1_RD_ENA` reader - Core0 PIF area1 read monitor enable"]
30pub type CORE_0_AREA_PIF_1_RD_ENA_R = crate::BitReader;
31#[doc = "Field `CORE_0_AREA_PIF_1_RD_ENA` writer - Core0 PIF area1 read monitor enable"]
32pub type CORE_0_AREA_PIF_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CORE_0_AREA_PIF_1_WR_ENA` reader - Core0 PIF area1 write monitor enable"]
34pub type CORE_0_AREA_PIF_1_WR_ENA_R = crate::BitReader;
35#[doc = "Field `CORE_0_AREA_PIF_1_WR_ENA` writer - Core0 PIF area1 write monitor enable"]
36pub type CORE_0_AREA_PIF_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CORE_0_SP_SPILL_MIN_ENA` reader - Core0 stackpoint overflow monitor enable"]
38pub type CORE_0_SP_SPILL_MIN_ENA_R = crate::BitReader;
39#[doc = "Field `CORE_0_SP_SPILL_MIN_ENA` writer - Core0 stackpoint overflow monitor enable"]
40pub type CORE_0_SP_SPILL_MIN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CORE_0_SP_SPILL_MAX_ENA` reader - Core0 stackpoint underflow monitor enable"]
42pub type CORE_0_SP_SPILL_MAX_ENA_R = crate::BitReader;
43#[doc = "Field `CORE_0_SP_SPILL_MAX_ENA` writer - Core0 stackpoint underflow monitor enable"]
44pub type CORE_0_SP_SPILL_MAX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_ENA` reader - IBUS busy monitor enable"]
46pub type CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader;
47#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_ENA` writer - IBUS busy monitor enable"]
48pub type CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_ENA` reader - DBUS busy monitor enbale"]
50pub type CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader;
51#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_ENA` writer - DBUS busy monitor enbale"]
52pub type CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54    #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"]
55    #[inline(always)]
56    pub fn core_0_area_dram0_0_rd_ena(&self) -> CORE_0_AREA_DRAM0_0_RD_ENA_R {
57        CORE_0_AREA_DRAM0_0_RD_ENA_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - Core0 dram0 area0 write monitor enable"]
60    #[inline(always)]
61    pub fn core_0_area_dram0_0_wr_ena(&self) -> CORE_0_AREA_DRAM0_0_WR_ENA_R {
62        CORE_0_AREA_DRAM0_0_WR_ENA_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bit 2 - Core0 dram0 area1 read monitor enable"]
65    #[inline(always)]
66    pub fn core_0_area_dram0_1_rd_ena(&self) -> CORE_0_AREA_DRAM0_1_RD_ENA_R {
67        CORE_0_AREA_DRAM0_1_RD_ENA_R::new(((self.bits >> 2) & 1) != 0)
68    }
69    #[doc = "Bit 3 - Core0 dram0 area1 write monitor enable"]
70    #[inline(always)]
71    pub fn core_0_area_dram0_1_wr_ena(&self) -> CORE_0_AREA_DRAM0_1_WR_ENA_R {
72        CORE_0_AREA_DRAM0_1_WR_ENA_R::new(((self.bits >> 3) & 1) != 0)
73    }
74    #[doc = "Bit 4 - Core0 PIF area0 read monitor enable"]
75    #[inline(always)]
76    pub fn core_0_area_pif_0_rd_ena(&self) -> CORE_0_AREA_PIF_0_RD_ENA_R {
77        CORE_0_AREA_PIF_0_RD_ENA_R::new(((self.bits >> 4) & 1) != 0)
78    }
79    #[doc = "Bit 5 - Core0 PIF area0 write monitor enable"]
80    #[inline(always)]
81    pub fn core_0_area_pif_0_wr_ena(&self) -> CORE_0_AREA_PIF_0_WR_ENA_R {
82        CORE_0_AREA_PIF_0_WR_ENA_R::new(((self.bits >> 5) & 1) != 0)
83    }
84    #[doc = "Bit 6 - Core0 PIF area1 read monitor enable"]
85    #[inline(always)]
86    pub fn core_0_area_pif_1_rd_ena(&self) -> CORE_0_AREA_PIF_1_RD_ENA_R {
87        CORE_0_AREA_PIF_1_RD_ENA_R::new(((self.bits >> 6) & 1) != 0)
88    }
89    #[doc = "Bit 7 - Core0 PIF area1 write monitor enable"]
90    #[inline(always)]
91    pub fn core_0_area_pif_1_wr_ena(&self) -> CORE_0_AREA_PIF_1_WR_ENA_R {
92        CORE_0_AREA_PIF_1_WR_ENA_R::new(((self.bits >> 7) & 1) != 0)
93    }
94    #[doc = "Bit 8 - Core0 stackpoint overflow monitor enable"]
95    #[inline(always)]
96    pub fn core_0_sp_spill_min_ena(&self) -> CORE_0_SP_SPILL_MIN_ENA_R {
97        CORE_0_SP_SPILL_MIN_ENA_R::new(((self.bits >> 8) & 1) != 0)
98    }
99    #[doc = "Bit 9 - Core0 stackpoint underflow monitor enable"]
100    #[inline(always)]
101    pub fn core_0_sp_spill_max_ena(&self) -> CORE_0_SP_SPILL_MAX_ENA_R {
102        CORE_0_SP_SPILL_MAX_ENA_R::new(((self.bits >> 9) & 1) != 0)
103    }
104    #[doc = "Bit 10 - IBUS busy monitor enable"]
105    #[inline(always)]
106    pub fn core_0_iram0_exception_monitor_ena(&self) -> CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R {
107        CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 10) & 1) != 0)
108    }
109    #[doc = "Bit 11 - DBUS busy monitor enbale"]
110    #[inline(always)]
111    pub fn core_0_dram0_exception_monitor_ena(&self) -> CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R {
112        CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 11) & 1) != 0)
113    }
114}
115#[cfg(feature = "impl-register-debug")]
116impl core::fmt::Debug for R {
117    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118        f.debug_struct("CORE_0_MONTR_ENA")
119            .field(
120                "core_0_area_dram0_0_rd_ena",
121                &self.core_0_area_dram0_0_rd_ena(),
122            )
123            .field(
124                "core_0_area_dram0_0_wr_ena",
125                &self.core_0_area_dram0_0_wr_ena(),
126            )
127            .field(
128                "core_0_area_dram0_1_rd_ena",
129                &self.core_0_area_dram0_1_rd_ena(),
130            )
131            .field(
132                "core_0_area_dram0_1_wr_ena",
133                &self.core_0_area_dram0_1_wr_ena(),
134            )
135            .field("core_0_area_pif_0_rd_ena", &self.core_0_area_pif_0_rd_ena())
136            .field("core_0_area_pif_0_wr_ena", &self.core_0_area_pif_0_wr_ena())
137            .field("core_0_area_pif_1_rd_ena", &self.core_0_area_pif_1_rd_ena())
138            .field("core_0_area_pif_1_wr_ena", &self.core_0_area_pif_1_wr_ena())
139            .field("core_0_sp_spill_min_ena", &self.core_0_sp_spill_min_ena())
140            .field("core_0_sp_spill_max_ena", &self.core_0_sp_spill_max_ena())
141            .field(
142                "core_0_iram0_exception_monitor_ena",
143                &self.core_0_iram0_exception_monitor_ena(),
144            )
145            .field(
146                "core_0_dram0_exception_monitor_ena",
147                &self.core_0_dram0_exception_monitor_ena(),
148            )
149            .finish()
150    }
151}
152impl W {
153    #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"]
154    #[inline(always)]
155    pub fn core_0_area_dram0_0_rd_ena(
156        &mut self,
157    ) -> CORE_0_AREA_DRAM0_0_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
158        CORE_0_AREA_DRAM0_0_RD_ENA_W::new(self, 0)
159    }
160    #[doc = "Bit 1 - Core0 dram0 area0 write monitor enable"]
161    #[inline(always)]
162    pub fn core_0_area_dram0_0_wr_ena(
163        &mut self,
164    ) -> CORE_0_AREA_DRAM0_0_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
165        CORE_0_AREA_DRAM0_0_WR_ENA_W::new(self, 1)
166    }
167    #[doc = "Bit 2 - Core0 dram0 area1 read monitor enable"]
168    #[inline(always)]
169    pub fn core_0_area_dram0_1_rd_ena(
170        &mut self,
171    ) -> CORE_0_AREA_DRAM0_1_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
172        CORE_0_AREA_DRAM0_1_RD_ENA_W::new(self, 2)
173    }
174    #[doc = "Bit 3 - Core0 dram0 area1 write monitor enable"]
175    #[inline(always)]
176    pub fn core_0_area_dram0_1_wr_ena(
177        &mut self,
178    ) -> CORE_0_AREA_DRAM0_1_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
179        CORE_0_AREA_DRAM0_1_WR_ENA_W::new(self, 3)
180    }
181    #[doc = "Bit 4 - Core0 PIF area0 read monitor enable"]
182    #[inline(always)]
183    pub fn core_0_area_pif_0_rd_ena(
184        &mut self,
185    ) -> CORE_0_AREA_PIF_0_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
186        CORE_0_AREA_PIF_0_RD_ENA_W::new(self, 4)
187    }
188    #[doc = "Bit 5 - Core0 PIF area0 write monitor enable"]
189    #[inline(always)]
190    pub fn core_0_area_pif_0_wr_ena(
191        &mut self,
192    ) -> CORE_0_AREA_PIF_0_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
193        CORE_0_AREA_PIF_0_WR_ENA_W::new(self, 5)
194    }
195    #[doc = "Bit 6 - Core0 PIF area1 read monitor enable"]
196    #[inline(always)]
197    pub fn core_0_area_pif_1_rd_ena(
198        &mut self,
199    ) -> CORE_0_AREA_PIF_1_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
200        CORE_0_AREA_PIF_1_RD_ENA_W::new(self, 6)
201    }
202    #[doc = "Bit 7 - Core0 PIF area1 write monitor enable"]
203    #[inline(always)]
204    pub fn core_0_area_pif_1_wr_ena(
205        &mut self,
206    ) -> CORE_0_AREA_PIF_1_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
207        CORE_0_AREA_PIF_1_WR_ENA_W::new(self, 7)
208    }
209    #[doc = "Bit 8 - Core0 stackpoint overflow monitor enable"]
210    #[inline(always)]
211    pub fn core_0_sp_spill_min_ena(&mut self) -> CORE_0_SP_SPILL_MIN_ENA_W<CORE_0_MONTR_ENA_SPEC> {
212        CORE_0_SP_SPILL_MIN_ENA_W::new(self, 8)
213    }
214    #[doc = "Bit 9 - Core0 stackpoint underflow monitor enable"]
215    #[inline(always)]
216    pub fn core_0_sp_spill_max_ena(&mut self) -> CORE_0_SP_SPILL_MAX_ENA_W<CORE_0_MONTR_ENA_SPEC> {
217        CORE_0_SP_SPILL_MAX_ENA_W::new(self, 9)
218    }
219    #[doc = "Bit 10 - IBUS busy monitor enable"]
220    #[inline(always)]
221    pub fn core_0_iram0_exception_monitor_ena(
222        &mut self,
223    ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
224        CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 10)
225    }
226    #[doc = "Bit 11 - DBUS busy monitor enbale"]
227    #[inline(always)]
228    pub fn core_0_dram0_exception_monitor_ena(
229        &mut self,
230    ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
231        CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 11)
232    }
233}
234#[doc = "core0 monitor enable configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_montr_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_montr_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
235pub struct CORE_0_MONTR_ENA_SPEC;
236impl crate::RegisterSpec for CORE_0_MONTR_ENA_SPEC {
237    type Ux = u32;
238}
239#[doc = "`read()` method returns [`core_0_montr_ena::R`](R) reader structure"]
240impl crate::Readable for CORE_0_MONTR_ENA_SPEC {}
241#[doc = "`write(|w| ..)` method takes [`core_0_montr_ena::W`](W) writer structure"]
242impl crate::Writable for CORE_0_MONTR_ENA_SPEC {
243    type Safety = crate::Unsafe;
244}
245#[doc = "`reset()` method sets CORE_0_MONTR_ENA to value 0"]
246impl crate::Resettable for CORE_0_MONTR_ENA_SPEC {}
esp32s3/assist_debug/core_0_montr_ena.rs

esp32s3/assist_debug/
core_0_montr_ena.rs
