1#[doc = "Register `CONF1` reader"]
2pub type R = crate::R<CONF1_SPEC>;
3#[doc = "Register `CONF1` writer"]
4pub type W = crate::W<CONF1_SPEC>;
5#[doc = "Field `CHECK_SUM_EN` reader - This is the enable bit to check header checksum when UHCI receives a data packet."]
6pub type CHECK_SUM_EN_R = crate::BitReader;
7#[doc = "Field `CHECK_SUM_EN` writer - This is the enable bit to check header checksum when UHCI receives a data packet."]
8pub type CHECK_SUM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CHECK_SEQ_EN` reader - This is the enable bit to check sequence number when UHCI receives a data packet."]
10pub type CHECK_SEQ_EN_R = crate::BitReader;
11#[doc = "Field `CHECK_SEQ_EN` writer - This is the enable bit to check sequence number when UHCI receives a data packet."]
12pub type CHECK_SEQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CRC_DISABLE` reader - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1."]
14pub type CRC_DISABLE_R = crate::BitReader;
15#[doc = "Field `CRC_DISABLE` writer - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1."]
16pub type CRC_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SAVE_HEAD` reader - Set this bit to save the packet header when HCI receives a data packet."]
18pub type SAVE_HEAD_R = crate::BitReader;
19#[doc = "Field `SAVE_HEAD` writer - Set this bit to save the packet header when HCI receives a data packet."]
20pub type SAVE_HEAD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TX_CHECK_SUM_RE` reader - Set this bit to encode the data packet with a checksum."]
22pub type TX_CHECK_SUM_RE_R = crate::BitReader;
23#[doc = "Field `TX_CHECK_SUM_RE` writer - Set this bit to encode the data packet with a checksum."]
24pub type TX_CHECK_SUM_RE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TX_ACK_NUM_RE` reader - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit."]
26pub type TX_ACK_NUM_RE_R = crate::BitReader;
27#[doc = "Field `TX_ACK_NUM_RE` writer - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit."]
28pub type TX_ACK_NUM_RE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `WAIT_SW_START` reader - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1."]
30pub type WAIT_SW_START_R = crate::BitReader;
31#[doc = "Field `WAIT_SW_START` writer - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1."]
32pub type WAIT_SW_START_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SW_START` reader - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
34pub type SW_START_R = crate::BitReader;
35#[doc = "Field `SW_START` writer - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
36pub type SW_START_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38 #[doc = "Bit 0 - This is the enable bit to check header checksum when UHCI receives a data packet."]
39 #[inline(always)]
40 pub fn check_sum_en(&self) -> CHECK_SUM_EN_R {
41 CHECK_SUM_EN_R::new((self.bits & 1) != 0)
42 }
43 #[doc = "Bit 1 - This is the enable bit to check sequence number when UHCI receives a data packet."]
44 #[inline(always)]
45 pub fn check_seq_en(&self) -> CHECK_SEQ_EN_R {
46 CHECK_SEQ_EN_R::new(((self.bits >> 1) & 1) != 0)
47 }
48 #[doc = "Bit 2 - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1."]
49 #[inline(always)]
50 pub fn crc_disable(&self) -> CRC_DISABLE_R {
51 CRC_DISABLE_R::new(((self.bits >> 2) & 1) != 0)
52 }
53 #[doc = "Bit 3 - Set this bit to save the packet header when HCI receives a data packet."]
54 #[inline(always)]
55 pub fn save_head(&self) -> SAVE_HEAD_R {
56 SAVE_HEAD_R::new(((self.bits >> 3) & 1) != 0)
57 }
58 #[doc = "Bit 4 - Set this bit to encode the data packet with a checksum."]
59 #[inline(always)]
60 pub fn tx_check_sum_re(&self) -> TX_CHECK_SUM_RE_R {
61 TX_CHECK_SUM_RE_R::new(((self.bits >> 4) & 1) != 0)
62 }
63 #[doc = "Bit 5 - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit."]
64 #[inline(always)]
65 pub fn tx_ack_num_re(&self) -> TX_ACK_NUM_RE_R {
66 TX_ACK_NUM_RE_R::new(((self.bits >> 5) & 1) != 0)
67 }
68 #[doc = "Bit 7 - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1."]
69 #[inline(always)]
70 pub fn wait_sw_start(&self) -> WAIT_SW_START_R {
71 WAIT_SW_START_R::new(((self.bits >> 7) & 1) != 0)
72 }
73 #[doc = "Bit 8 - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
74 #[inline(always)]
75 pub fn sw_start(&self) -> SW_START_R {
76 SW_START_R::new(((self.bits >> 8) & 1) != 0)
77 }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82 f.debug_struct("CONF1")
83 .field("check_sum_en", &self.check_sum_en())
84 .field("check_seq_en", &self.check_seq_en())
85 .field("crc_disable", &self.crc_disable())
86 .field("save_head", &self.save_head())
87 .field("tx_check_sum_re", &self.tx_check_sum_re())
88 .field("tx_ack_num_re", &self.tx_ack_num_re())
89 .field("wait_sw_start", &self.wait_sw_start())
90 .field("sw_start", &self.sw_start())
91 .finish()
92 }
93}
94impl W {
95 #[doc = "Bit 0 - This is the enable bit to check header checksum when UHCI receives a data packet."]
96 #[inline(always)]
97 pub fn check_sum_en(&mut self) -> CHECK_SUM_EN_W<CONF1_SPEC> {
98 CHECK_SUM_EN_W::new(self, 0)
99 }
100 #[doc = "Bit 1 - This is the enable bit to check sequence number when UHCI receives a data packet."]
101 #[inline(always)]
102 pub fn check_seq_en(&mut self) -> CHECK_SEQ_EN_W<CONF1_SPEC> {
103 CHECK_SEQ_EN_W::new(self, 1)
104 }
105 #[doc = "Bit 2 - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1."]
106 #[inline(always)]
107 pub fn crc_disable(&mut self) -> CRC_DISABLE_W<CONF1_SPEC> {
108 CRC_DISABLE_W::new(self, 2)
109 }
110 #[doc = "Bit 3 - Set this bit to save the packet header when HCI receives a data packet."]
111 #[inline(always)]
112 pub fn save_head(&mut self) -> SAVE_HEAD_W<CONF1_SPEC> {
113 SAVE_HEAD_W::new(self, 3)
114 }
115 #[doc = "Bit 4 - Set this bit to encode the data packet with a checksum."]
116 #[inline(always)]
117 pub fn tx_check_sum_re(&mut self) -> TX_CHECK_SUM_RE_W<CONF1_SPEC> {
118 TX_CHECK_SUM_RE_W::new(self, 4)
119 }
120 #[doc = "Bit 5 - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit."]
121 #[inline(always)]
122 pub fn tx_ack_num_re(&mut self) -> TX_ACK_NUM_RE_W<CONF1_SPEC> {
123 TX_ACK_NUM_RE_W::new(self, 5)
124 }
125 #[doc = "Bit 7 - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1."]
126 #[inline(always)]
127 pub fn wait_sw_start(&mut self) -> WAIT_SW_START_W<CONF1_SPEC> {
128 WAIT_SW_START_W::new(self, 7)
129 }
130 #[doc = "Bit 8 - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
131 #[inline(always)]
132 pub fn sw_start(&mut self) -> SW_START_W<CONF1_SPEC> {
133 SW_START_W::new(self, 8)
134 }
135}
136#[doc = "UHCI configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct CONF1_SPEC;
138impl crate::RegisterSpec for CONF1_SPEC {
139 type Ux = u32;
140}
141#[doc = "`read()` method returns [`conf1::R`](R) reader structure"]
142impl crate::Readable for CONF1_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"]
144impl crate::Writable for CONF1_SPEC {
145 type Safety = crate::Unsafe;
146}
147#[doc = "`reset()` method sets CONF1 to value 0x33"]
148impl crate::Resettable for CONF1_SPEC {
149 const RESET_VALUE: u32 = 0x33;
150}