esp32s3/system/
perip_clk_en1.rs

1#[doc = "Register `PERIP_CLK_EN1` reader"]
2pub type R = crate::R<PERIP_CLK_EN1_SPEC>;
3#[doc = "Register `PERIP_CLK_EN1` writer"]
4pub type W = crate::W<PERIP_CLK_EN1_SPEC>;
5#[doc = "Field `PERI_BACKUP_CLK_EN` reader - Set 1 to enable BACKUP clock"]
6pub type PERI_BACKUP_CLK_EN_R = crate::BitReader;
7#[doc = "Field `PERI_BACKUP_CLK_EN` writer - Set 1 to enable BACKUP clock"]
8pub type PERI_BACKUP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CRYPTO_AES_CLK_EN` reader - Set 1 to enable AES clock"]
10pub type CRYPTO_AES_CLK_EN_R = crate::BitReader;
11#[doc = "Field `CRYPTO_AES_CLK_EN` writer - Set 1 to enable AES clock"]
12pub type CRYPTO_AES_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CRYPTO_SHA_CLK_EN` reader - Set 1 to enable SHA clock"]
14pub type CRYPTO_SHA_CLK_EN_R = crate::BitReader;
15#[doc = "Field `CRYPTO_SHA_CLK_EN` writer - Set 1 to enable SHA clock"]
16pub type CRYPTO_SHA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CRYPTO_RSA_CLK_EN` reader - Set 1 to enable RSA clock"]
18pub type CRYPTO_RSA_CLK_EN_R = crate::BitReader;
19#[doc = "Field `CRYPTO_RSA_CLK_EN` writer - Set 1 to enable RSA clock"]
20pub type CRYPTO_RSA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CRYPTO_DS_CLK_EN` reader - Set 1 to enable DS clock"]
22pub type CRYPTO_DS_CLK_EN_R = crate::BitReader;
23#[doc = "Field `CRYPTO_DS_CLK_EN` writer - Set 1 to enable DS clock"]
24pub type CRYPTO_DS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CRYPTO_HMAC_CLK_EN` reader - Set 1 to enable HMAC clock"]
26pub type CRYPTO_HMAC_CLK_EN_R = crate::BitReader;
27#[doc = "Field `CRYPTO_HMAC_CLK_EN` writer - Set 1 to enable HMAC clock"]
28pub type CRYPTO_HMAC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DMA_CLK_EN` reader - Set 1 to enable DMA clock"]
30pub type DMA_CLK_EN_R = crate::BitReader;
31#[doc = "Field `DMA_CLK_EN` writer - Set 1 to enable DMA clock"]
32pub type DMA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SDIO_HOST_CLK_EN` reader - Set 1 to enable SDIO_HOST clock"]
34pub type SDIO_HOST_CLK_EN_R = crate::BitReader;
35#[doc = "Field `SDIO_HOST_CLK_EN` writer - Set 1 to enable SDIO_HOST clock"]
36pub type SDIO_HOST_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `LCD_CAM_CLK_EN` reader - Set 1 to enable LCD_CAM clock"]
38pub type LCD_CAM_CLK_EN_R = crate::BitReader;
39#[doc = "Field `LCD_CAM_CLK_EN` writer - Set 1 to enable LCD_CAM clock"]
40pub type LCD_CAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `UART2_CLK_EN` reader - Set 1 to enable UART2 clock"]
42pub type UART2_CLK_EN_R = crate::BitReader;
43#[doc = "Field `UART2_CLK_EN` writer - Set 1 to enable UART2 clock"]
44pub type UART2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `USB_DEVICE_CLK_EN` reader - Set 1 to enable USB_DEVICE clock"]
46pub type USB_DEVICE_CLK_EN_R = crate::BitReader;
47#[doc = "Field `USB_DEVICE_CLK_EN` writer - Set 1 to enable USB_DEVICE clock"]
48pub type USB_DEVICE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50    #[doc = "Bit 0 - Set 1 to enable BACKUP clock"]
51    #[inline(always)]
52    pub fn peri_backup_clk_en(&self) -> PERI_BACKUP_CLK_EN_R {
53        PERI_BACKUP_CLK_EN_R::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bit 1 - Set 1 to enable AES clock"]
56    #[inline(always)]
57    pub fn crypto_aes_clk_en(&self) -> CRYPTO_AES_CLK_EN_R {
58        CRYPTO_AES_CLK_EN_R::new(((self.bits >> 1) & 1) != 0)
59    }
60    #[doc = "Bit 2 - Set 1 to enable SHA clock"]
61    #[inline(always)]
62    pub fn crypto_sha_clk_en(&self) -> CRYPTO_SHA_CLK_EN_R {
63        CRYPTO_SHA_CLK_EN_R::new(((self.bits >> 2) & 1) != 0)
64    }
65    #[doc = "Bit 3 - Set 1 to enable RSA clock"]
66    #[inline(always)]
67    pub fn crypto_rsa_clk_en(&self) -> CRYPTO_RSA_CLK_EN_R {
68        CRYPTO_RSA_CLK_EN_R::new(((self.bits >> 3) & 1) != 0)
69    }
70    #[doc = "Bit 4 - Set 1 to enable DS clock"]
71    #[inline(always)]
72    pub fn crypto_ds_clk_en(&self) -> CRYPTO_DS_CLK_EN_R {
73        CRYPTO_DS_CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
74    }
75    #[doc = "Bit 5 - Set 1 to enable HMAC clock"]
76    #[inline(always)]
77    pub fn crypto_hmac_clk_en(&self) -> CRYPTO_HMAC_CLK_EN_R {
78        CRYPTO_HMAC_CLK_EN_R::new(((self.bits >> 5) & 1) != 0)
79    }
80    #[doc = "Bit 6 - Set 1 to enable DMA clock"]
81    #[inline(always)]
82    pub fn dma_clk_en(&self) -> DMA_CLK_EN_R {
83        DMA_CLK_EN_R::new(((self.bits >> 6) & 1) != 0)
84    }
85    #[doc = "Bit 7 - Set 1 to enable SDIO_HOST clock"]
86    #[inline(always)]
87    pub fn sdio_host_clk_en(&self) -> SDIO_HOST_CLK_EN_R {
88        SDIO_HOST_CLK_EN_R::new(((self.bits >> 7) & 1) != 0)
89    }
90    #[doc = "Bit 8 - Set 1 to enable LCD_CAM clock"]
91    #[inline(always)]
92    pub fn lcd_cam_clk_en(&self) -> LCD_CAM_CLK_EN_R {
93        LCD_CAM_CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
94    }
95    #[doc = "Bit 9 - Set 1 to enable UART2 clock"]
96    #[inline(always)]
97    pub fn uart2_clk_en(&self) -> UART2_CLK_EN_R {
98        UART2_CLK_EN_R::new(((self.bits >> 9) & 1) != 0)
99    }
100    #[doc = "Bit 10 - Set 1 to enable USB_DEVICE clock"]
101    #[inline(always)]
102    pub fn usb_device_clk_en(&self) -> USB_DEVICE_CLK_EN_R {
103        USB_DEVICE_CLK_EN_R::new(((self.bits >> 10) & 1) != 0)
104    }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109        f.debug_struct("PERIP_CLK_EN1")
110            .field("peri_backup_clk_en", &self.peri_backup_clk_en())
111            .field("crypto_aes_clk_en", &self.crypto_aes_clk_en())
112            .field("crypto_sha_clk_en", &self.crypto_sha_clk_en())
113            .field("crypto_rsa_clk_en", &self.crypto_rsa_clk_en())
114            .field("crypto_ds_clk_en", &self.crypto_ds_clk_en())
115            .field("crypto_hmac_clk_en", &self.crypto_hmac_clk_en())
116            .field("dma_clk_en", &self.dma_clk_en())
117            .field("sdio_host_clk_en", &self.sdio_host_clk_en())
118            .field("lcd_cam_clk_en", &self.lcd_cam_clk_en())
119            .field("uart2_clk_en", &self.uart2_clk_en())
120            .field("usb_device_clk_en", &self.usb_device_clk_en())
121            .finish()
122    }
123}
124impl W {
125    #[doc = "Bit 0 - Set 1 to enable BACKUP clock"]
126    #[inline(always)]
127    pub fn peri_backup_clk_en(&mut self) -> PERI_BACKUP_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
128        PERI_BACKUP_CLK_EN_W::new(self, 0)
129    }
130    #[doc = "Bit 1 - Set 1 to enable AES clock"]
131    #[inline(always)]
132    pub fn crypto_aes_clk_en(&mut self) -> CRYPTO_AES_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
133        CRYPTO_AES_CLK_EN_W::new(self, 1)
134    }
135    #[doc = "Bit 2 - Set 1 to enable SHA clock"]
136    #[inline(always)]
137    pub fn crypto_sha_clk_en(&mut self) -> CRYPTO_SHA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
138        CRYPTO_SHA_CLK_EN_W::new(self, 2)
139    }
140    #[doc = "Bit 3 - Set 1 to enable RSA clock"]
141    #[inline(always)]
142    pub fn crypto_rsa_clk_en(&mut self) -> CRYPTO_RSA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
143        CRYPTO_RSA_CLK_EN_W::new(self, 3)
144    }
145    #[doc = "Bit 4 - Set 1 to enable DS clock"]
146    #[inline(always)]
147    pub fn crypto_ds_clk_en(&mut self) -> CRYPTO_DS_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
148        CRYPTO_DS_CLK_EN_W::new(self, 4)
149    }
150    #[doc = "Bit 5 - Set 1 to enable HMAC clock"]
151    #[inline(always)]
152    pub fn crypto_hmac_clk_en(&mut self) -> CRYPTO_HMAC_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
153        CRYPTO_HMAC_CLK_EN_W::new(self, 5)
154    }
155    #[doc = "Bit 6 - Set 1 to enable DMA clock"]
156    #[inline(always)]
157    pub fn dma_clk_en(&mut self) -> DMA_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
158        DMA_CLK_EN_W::new(self, 6)
159    }
160    #[doc = "Bit 7 - Set 1 to enable SDIO_HOST clock"]
161    #[inline(always)]
162    pub fn sdio_host_clk_en(&mut self) -> SDIO_HOST_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
163        SDIO_HOST_CLK_EN_W::new(self, 7)
164    }
165    #[doc = "Bit 8 - Set 1 to enable LCD_CAM clock"]
166    #[inline(always)]
167    pub fn lcd_cam_clk_en(&mut self) -> LCD_CAM_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
168        LCD_CAM_CLK_EN_W::new(self, 8)
169    }
170    #[doc = "Bit 9 - Set 1 to enable UART2 clock"]
171    #[inline(always)]
172    pub fn uart2_clk_en(&mut self) -> UART2_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
173        UART2_CLK_EN_W::new(self, 9)
174    }
175    #[doc = "Bit 10 - Set 1 to enable USB_DEVICE clock"]
176    #[inline(always)]
177    pub fn usb_device_clk_en(&mut self) -> USB_DEVICE_CLK_EN_W<PERIP_CLK_EN1_SPEC> {
178        USB_DEVICE_CLK_EN_W::new(self, 10)
179    }
180}
181#[doc = "peripheral clock configuration regsiter 1\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_clk_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_clk_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct PERIP_CLK_EN1_SPEC;
183impl crate::RegisterSpec for PERIP_CLK_EN1_SPEC {
184    type Ux = u32;
185}
186#[doc = "`read()` method returns [`perip_clk_en1::R`](R) reader structure"]
187impl crate::Readable for PERIP_CLK_EN1_SPEC {}
188#[doc = "`write(|w| ..)` method takes [`perip_clk_en1::W`](W) writer structure"]
189impl crate::Writable for PERIP_CLK_EN1_SPEC {
190    type Safety = crate::Unsafe;
191}
192#[doc = "`reset()` method sets PERIP_CLK_EN1 to value 0x0600"]
193impl crate::Resettable for PERIP_CLK_EN1_SPEC {
194    const RESET_VALUE: u32 = 0x0600;
195}
esp32s3/system/perip_clk_en1.rs

esp32s3/system/
perip_clk_en1.rs
