esp32s3/spi0/
spi_smem_timing_cali.rs

1#[doc = "Register `SPI_SMEM_TIMING_CALI` reader"]
2pub type R = crate::R<SPI_SMEM_TIMING_CALI_SPEC>;
3#[doc = "Register `SPI_SMEM_TIMING_CALI` writer"]
4pub type W = crate::W<SPI_SMEM_TIMING_CALI_SPEC>;
5#[doc = "Field `SPI_SMEM_TIMING_CLK_ENA` reader - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL."]
6pub type SPI_SMEM_TIMING_CLK_ENA_R = crate::BitReader;
7#[doc = "Field `SPI_SMEM_TIMING_CLK_ENA` writer - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL."]
8pub type SPI_SMEM_TIMING_CLK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI_SMEM_TIMING_CALI` reader - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations."]
10pub type SPI_SMEM_TIMING_CALI_R = crate::BitReader;
11#[doc = "Field `SPI_SMEM_TIMING_CALI` writer - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations."]
12pub type SPI_SMEM_TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SPI_SMEM_EXTRA_DUMMY_CYCLELEN` reader - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set."]
14pub type SPI_SMEM_EXTRA_DUMMY_CYCLELEN_R = crate::FieldReader;
15#[doc = "Field `SPI_SMEM_EXTRA_DUMMY_CYCLELEN` writer - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set."]
16pub type SPI_SMEM_EXTRA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17impl R {
18    #[doc = "Bit 0 - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL."]
19    #[inline(always)]
20    pub fn spi_smem_timing_clk_ena(&self) -> SPI_SMEM_TIMING_CLK_ENA_R {
21        SPI_SMEM_TIMING_CLK_ENA_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations."]
24    #[inline(always)]
25    pub fn spi_smem_timing_cali(&self) -> SPI_SMEM_TIMING_CALI_R {
26        SPI_SMEM_TIMING_CALI_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bits 2:4 - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set."]
29    #[inline(always)]
30    pub fn spi_smem_extra_dummy_cyclelen(&self) -> SPI_SMEM_EXTRA_DUMMY_CYCLELEN_R {
31        SPI_SMEM_EXTRA_DUMMY_CYCLELEN_R::new(((self.bits >> 2) & 7) as u8)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("SPI_SMEM_TIMING_CALI")
38            .field("spi_smem_timing_clk_ena", &self.spi_smem_timing_clk_ena())
39            .field("spi_smem_timing_cali", &self.spi_smem_timing_cali())
40            .field(
41                "spi_smem_extra_dummy_cyclelen",
42                &self.spi_smem_extra_dummy_cyclelen(),
43            )
44            .finish()
45    }
46}
47impl W {
48    #[doc = "Bit 0 - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL."]
49    #[inline(always)]
50    pub fn spi_smem_timing_clk_ena(
51        &mut self,
52    ) -> SPI_SMEM_TIMING_CLK_ENA_W<SPI_SMEM_TIMING_CALI_SPEC> {
53        SPI_SMEM_TIMING_CLK_ENA_W::new(self, 0)
54    }
55    #[doc = "Bit 1 - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations."]
56    #[inline(always)]
57    pub fn spi_smem_timing_cali(&mut self) -> SPI_SMEM_TIMING_CALI_W<SPI_SMEM_TIMING_CALI_SPEC> {
58        SPI_SMEM_TIMING_CALI_W::new(self, 1)
59    }
60    #[doc = "Bits 2:4 - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set."]
61    #[inline(always)]
62    pub fn spi_smem_extra_dummy_cyclelen(
63        &mut self,
64    ) -> SPI_SMEM_EXTRA_DUMMY_CYCLELEN_W<SPI_SMEM_TIMING_CALI_SPEC> {
65        SPI_SMEM_EXTRA_DUMMY_CYCLELEN_W::new(self, 2)
66    }
67}
68#[doc = "SPI0 Ext_RAM timing compensation register.\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_smem_timing_cali::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_smem_timing_cali::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
69pub struct SPI_SMEM_TIMING_CALI_SPEC;
70impl crate::RegisterSpec for SPI_SMEM_TIMING_CALI_SPEC {
71    type Ux = u32;
72}
73#[doc = "`read()` method returns [`spi_smem_timing_cali::R`](R) reader structure"]
74impl crate::Readable for SPI_SMEM_TIMING_CALI_SPEC {}
75#[doc = "`write(|w| ..)` method takes [`spi_smem_timing_cali::W`](W) writer structure"]
76impl crate::Writable for SPI_SMEM_TIMING_CALI_SPEC {
77    type Safety = crate::Unsafe;
78}
79#[doc = "`reset()` method sets SPI_SMEM_TIMING_CALI to value 0"]
80impl crate::Resettable for SPI_SMEM_TIMING_CALI_SPEC {}
esp32s3/spi0/spi_smem_timing_cali.rs

esp32s3/spi0/
spi_smem_timing_cali.rs
