esp32s3/spi0/
spi_smem_ac.rs1#[doc = "Register `SPI_SMEM_AC` reader"]
2pub type R = crate::R<SPI_SMEM_AC_SPEC>;
3#[doc = "Register `SPI_SMEM_AC` writer"]
4pub type W = crate::W<SPI_SMEM_AC_SPEC>;
5#[doc = "Field `SPI_SMEM_CS_SETUP` reader - Set this bit to keep SPI_CS low when MSPI is in PREP state."]
6pub type SPI_SMEM_CS_SETUP_R = crate::BitReader;
7#[doc = "Field `SPI_SMEM_CS_SETUP` writer - Set this bit to keep SPI_CS low when MSPI is in PREP state."]
8pub type SPI_SMEM_CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI_SMEM_CS_HOLD` reader - Set this bit to keep SPI_CS low when MSPI is in DONE state."]
10pub type SPI_SMEM_CS_HOLD_R = crate::BitReader;
11#[doc = "Field `SPI_SMEM_CS_HOLD` writer - Set this bit to keep SPI_CS low when MSPI is in DONE state."]
12pub type SPI_SMEM_CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SPI_SMEM_CS_SETUP_TIME` reader - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
14pub type SPI_SMEM_CS_SETUP_TIME_R = crate::FieldReader;
15#[doc = "Field `SPI_SMEM_CS_SETUP_TIME` writer - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
16pub type SPI_SMEM_CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
17#[doc = "Field `SPI_SMEM_CS_HOLD_TIME` reader - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
18pub type SPI_SMEM_CS_HOLD_TIME_R = crate::FieldReader;
19#[doc = "Field `SPI_SMEM_CS_HOLD_TIME` writer - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
20pub type SPI_SMEM_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
21#[doc = "Field `SPI_SMEM_ECC_CS_HOLD_TIME` reader - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM."]
22pub type SPI_SMEM_ECC_CS_HOLD_TIME_R = crate::FieldReader;
23#[doc = "Field `SPI_SMEM_ECC_CS_HOLD_TIME` writer - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM."]
24pub type SPI_SMEM_ECC_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25#[doc = "Field `SPI_SMEM_ECC_SKIP_PAGE_CORNER` reader - 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM."]
26pub type SPI_SMEM_ECC_SKIP_PAGE_CORNER_R = crate::BitReader;
27#[doc = "Field `SPI_SMEM_ECC_SKIP_PAGE_CORNER` writer - 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM."]
28pub type SPI_SMEM_ECC_SKIP_PAGE_CORNER_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SPI_SMEM_ECC_16TO18_BYTE_EN` reader - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM."]
30pub type SPI_SMEM_ECC_16TO18_BYTE_EN_R = crate::BitReader;
31#[doc = "Field `SPI_SMEM_ECC_16TO18_BYTE_EN` writer - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM."]
32pub type SPI_SMEM_ECC_16TO18_BYTE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SPI_SMEM_ECC_ERR_INT_EN` reader - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."]
34pub type SPI_SMEM_ECC_ERR_INT_EN_R = crate::BitReader;
35#[doc = "Field `SPI_SMEM_ECC_ERR_INT_EN` writer - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."]
36pub type SPI_SMEM_ECC_ERR_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SPI_SMEM_CS_HOLD_DELAY` reader - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
38pub type SPI_SMEM_CS_HOLD_DELAY_R = crate::FieldReader;
39#[doc = "Field `SPI_SMEM_CS_HOLD_DELAY` writer - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
40pub type SPI_SMEM_CS_HOLD_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
41impl R {
42 #[doc = "Bit 0 - Set this bit to keep SPI_CS low when MSPI is in PREP state."]
43 #[inline(always)]
44 pub fn spi_smem_cs_setup(&self) -> SPI_SMEM_CS_SETUP_R {
45 SPI_SMEM_CS_SETUP_R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - Set this bit to keep SPI_CS low when MSPI is in DONE state."]
48 #[inline(always)]
49 pub fn spi_smem_cs_hold(&self) -> SPI_SMEM_CS_HOLD_R {
50 SPI_SMEM_CS_HOLD_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bits 2:6 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
53 #[inline(always)]
54 pub fn spi_smem_cs_setup_time(&self) -> SPI_SMEM_CS_SETUP_TIME_R {
55 SPI_SMEM_CS_SETUP_TIME_R::new(((self.bits >> 2) & 0x1f) as u8)
56 }
57 #[doc = "Bits 7:11 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
58 #[inline(always)]
59 pub fn spi_smem_cs_hold_time(&self) -> SPI_SMEM_CS_HOLD_TIME_R {
60 SPI_SMEM_CS_HOLD_TIME_R::new(((self.bits >> 7) & 0x1f) as u8)
61 }
62 #[doc = "Bits 12:14 - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM."]
63 #[inline(always)]
64 pub fn spi_smem_ecc_cs_hold_time(&self) -> SPI_SMEM_ECC_CS_HOLD_TIME_R {
65 SPI_SMEM_ECC_CS_HOLD_TIME_R::new(((self.bits >> 12) & 7) as u8)
66 }
67 #[doc = "Bit 15 - 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM."]
68 #[inline(always)]
69 pub fn spi_smem_ecc_skip_page_corner(&self) -> SPI_SMEM_ECC_SKIP_PAGE_CORNER_R {
70 SPI_SMEM_ECC_SKIP_PAGE_CORNER_R::new(((self.bits >> 15) & 1) != 0)
71 }
72 #[doc = "Bit 16 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM."]
73 #[inline(always)]
74 pub fn spi_smem_ecc_16to18_byte_en(&self) -> SPI_SMEM_ECC_16TO18_BYTE_EN_R {
75 SPI_SMEM_ECC_16TO18_BYTE_EN_R::new(((self.bits >> 16) & 1) != 0)
76 }
77 #[doc = "Bit 24 - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."]
78 #[inline(always)]
79 pub fn spi_smem_ecc_err_int_en(&self) -> SPI_SMEM_ECC_ERR_INT_EN_R {
80 SPI_SMEM_ECC_ERR_INT_EN_R::new(((self.bits >> 24) & 1) != 0)
81 }
82 #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
83 #[inline(always)]
84 pub fn spi_smem_cs_hold_delay(&self) -> SPI_SMEM_CS_HOLD_DELAY_R {
85 SPI_SMEM_CS_HOLD_DELAY_R::new(((self.bits >> 25) & 0x3f) as u8)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("SPI_SMEM_AC")
92 .field("spi_smem_cs_setup", &self.spi_smem_cs_setup())
93 .field("spi_smem_cs_hold", &self.spi_smem_cs_hold())
94 .field("spi_smem_cs_setup_time", &self.spi_smem_cs_setup_time())
95 .field("spi_smem_cs_hold_time", &self.spi_smem_cs_hold_time())
96 .field(
97 "spi_smem_ecc_cs_hold_time",
98 &self.spi_smem_ecc_cs_hold_time(),
99 )
100 .field(
101 "spi_smem_ecc_skip_page_corner",
102 &self.spi_smem_ecc_skip_page_corner(),
103 )
104 .field(
105 "spi_smem_ecc_16to18_byte_en",
106 &self.spi_smem_ecc_16to18_byte_en(),
107 )
108 .field("spi_smem_ecc_err_int_en", &self.spi_smem_ecc_err_int_en())
109 .field("spi_smem_cs_hold_delay", &self.spi_smem_cs_hold_delay())
110 .finish()
111 }
112}
113impl W {
114 #[doc = "Bit 0 - Set this bit to keep SPI_CS low when MSPI is in PREP state."]
115 #[inline(always)]
116 pub fn spi_smem_cs_setup(&mut self) -> SPI_SMEM_CS_SETUP_W<SPI_SMEM_AC_SPEC> {
117 SPI_SMEM_CS_SETUP_W::new(self, 0)
118 }
119 #[doc = "Bit 1 - Set this bit to keep SPI_CS low when MSPI is in DONE state."]
120 #[inline(always)]
121 pub fn spi_smem_cs_hold(&mut self) -> SPI_SMEM_CS_HOLD_W<SPI_SMEM_AC_SPEC> {
122 SPI_SMEM_CS_HOLD_W::new(self, 1)
123 }
124 #[doc = "Bits 2:6 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
125 #[inline(always)]
126 pub fn spi_smem_cs_setup_time(&mut self) -> SPI_SMEM_CS_SETUP_TIME_W<SPI_SMEM_AC_SPEC> {
127 SPI_SMEM_CS_SETUP_TIME_W::new(self, 2)
128 }
129 #[doc = "Bits 7:11 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
130 #[inline(always)]
131 pub fn spi_smem_cs_hold_time(&mut self) -> SPI_SMEM_CS_HOLD_TIME_W<SPI_SMEM_AC_SPEC> {
132 SPI_SMEM_CS_HOLD_TIME_W::new(self, 7)
133 }
134 #[doc = "Bits 12:14 - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM."]
135 #[inline(always)]
136 pub fn spi_smem_ecc_cs_hold_time(&mut self) -> SPI_SMEM_ECC_CS_HOLD_TIME_W<SPI_SMEM_AC_SPEC> {
137 SPI_SMEM_ECC_CS_HOLD_TIME_W::new(self, 12)
138 }
139 #[doc = "Bit 15 - 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM."]
140 #[inline(always)]
141 pub fn spi_smem_ecc_skip_page_corner(
142 &mut self,
143 ) -> SPI_SMEM_ECC_SKIP_PAGE_CORNER_W<SPI_SMEM_AC_SPEC> {
144 SPI_SMEM_ECC_SKIP_PAGE_CORNER_W::new(self, 15)
145 }
146 #[doc = "Bit 16 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM."]
147 #[inline(always)]
148 pub fn spi_smem_ecc_16to18_byte_en(
149 &mut self,
150 ) -> SPI_SMEM_ECC_16TO18_BYTE_EN_W<SPI_SMEM_AC_SPEC> {
151 SPI_SMEM_ECC_16TO18_BYTE_EN_W::new(self, 16)
152 }
153 #[doc = "Bit 24 - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."]
154 #[inline(always)]
155 pub fn spi_smem_ecc_err_int_en(&mut self) -> SPI_SMEM_ECC_ERR_INT_EN_W<SPI_SMEM_AC_SPEC> {
156 SPI_SMEM_ECC_ERR_INT_EN_W::new(self, 24)
157 }
158 #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
159 #[inline(always)]
160 pub fn spi_smem_cs_hold_delay(&mut self) -> SPI_SMEM_CS_HOLD_DELAY_W<SPI_SMEM_AC_SPEC> {
161 SPI_SMEM_CS_HOLD_DELAY_W::new(self, 25)
162 }
163}
164#[doc = "MSPI external RAM ECC and SPI CS timing control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_smem_ac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_smem_ac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
165pub struct SPI_SMEM_AC_SPEC;
166impl crate::RegisterSpec for SPI_SMEM_AC_SPEC {
167 type Ux = u32;
168}
169#[doc = "`read()` method returns [`spi_smem_ac::R`](R) reader structure"]
170impl crate::Readable for SPI_SMEM_AC_SPEC {}
171#[doc = "`write(|w| ..)` method takes [`spi_smem_ac::W`](W) writer structure"]
172impl crate::Writable for SPI_SMEM_AC_SPEC {
173 type Safety = crate::Unsafe;
174}
175#[doc = "`reset()` method sets SPI_SMEM_AC to value 0xb084"]
176impl crate::Resettable for SPI_SMEM_AC_SPEC {
177 const RESET_VALUE: u32 = 0xb084;
178}