esp32s3/spi0/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `TOTAL_TRANS_END` writer - The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
4pub type TOTAL_TRANS_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `ECC_ERR` writer - The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit."]
6pub type ECC_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[cfg(feature = "impl-register-debug")]
8impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        write!(f, "(not readable)")
11    }
12}
13impl W {
14    #[doc = "Bit 2 - The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
15    #[inline(always)]
16    pub fn total_trans_end(&mut self) -> TOTAL_TRANS_END_W<INT_CLR_SPEC> {
17        TOTAL_TRANS_END_W::new(self, 2)
18    }
19    #[doc = "Bit 4 - The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit."]
20    #[inline(always)]
21    pub fn ecc_err(&mut self) -> ECC_ERR_W<INT_CLR_SPEC> {
22        ECC_ERR_W::new(self, 4)
23    }
24}
25#[doc = "SPI1 interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26pub struct INT_CLR_SPEC;
27impl crate::RegisterSpec for INT_CLR_SPEC {
28    type Ux = u32;
29}
30#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
31impl crate::Writable for INT_CLR_SPEC {
32    type Safety = crate::Unsafe;
33    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x14;
34}
35#[doc = "`reset()` method sets INT_CLR to value 0"]
36impl crate::Resettable for INT_CLR_SPEC {}
esp32s3/spi0/int_clr.rs

esp32s3/spi0/
int_clr.rs
