1#[doc = "Register `DIN_NUM` reader"]
2pub type R = crate::R<DIN_NUM_SPEC>;
3#[doc = "Register `DIN_NUM` writer"]
4pub type W = crate::W<DIN_NUM_SPEC>;
5#[doc = "Field `DIN0_NUM` reader - SPI_D input delay number."]
6pub type DIN0_NUM_R = crate::FieldReader;
7#[doc = "Field `DIN0_NUM` writer - SPI_D input delay number."]
8pub type DIN0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `DIN1_NUM` reader - SPI_Q input delay number."]
10pub type DIN1_NUM_R = crate::FieldReader;
11#[doc = "Field `DIN1_NUM` writer - SPI_Q input delay number."]
12pub type DIN1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `DIN2_NUM` reader - SPI_WP input delay number."]
14pub type DIN2_NUM_R = crate::FieldReader;
15#[doc = "Field `DIN2_NUM` writer - SPI_WP input delay number."]
16pub type DIN2_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `DIN3_NUM` reader - SPI_HD input delay number."]
18pub type DIN3_NUM_R = crate::FieldReader;
19#[doc = "Field `DIN3_NUM` writer - SPI_HD input delay number."]
20pub type DIN3_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `DIN4_NUM` reader - SPI_IO4 input delay number."]
22pub type DIN4_NUM_R = crate::FieldReader;
23#[doc = "Field `DIN4_NUM` writer - SPI_IO4 input delay number."]
24pub type DIN4_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `DIN5_NUM` reader - SPI_IO5 input delay number."]
26pub type DIN5_NUM_R = crate::FieldReader;
27#[doc = "Field `DIN5_NUM` writer - SPI_IO5 input delay number."]
28pub type DIN5_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `DIN6_NUM` reader - SPI_IO6 input delay number."]
30pub type DIN6_NUM_R = crate::FieldReader;
31#[doc = "Field `DIN6_NUM` writer - SPI_IO6 input delay number."]
32pub type DIN6_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `DIN7_NUM` reader - SPI_IO7 input delay number."]
34pub type DIN7_NUM_R = crate::FieldReader;
35#[doc = "Field `DIN7_NUM` writer - SPI_IO7 input delay number."]
36pub type DIN7_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `DINS_NUM` reader - SPI_DQS input delay number."]
38pub type DINS_NUM_R = crate::FieldReader;
39#[doc = "Field `DINS_NUM` writer - SPI_DQS input delay number."]
40pub type DINS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41impl R {
42 #[doc = "Bits 0:1 - SPI_D input delay number."]
43 #[inline(always)]
44 pub fn din0_num(&self) -> DIN0_NUM_R {
45 DIN0_NUM_R::new((self.bits & 3) as u8)
46 }
47 #[doc = "Bits 2:3 - SPI_Q input delay number."]
48 #[inline(always)]
49 pub fn din1_num(&self) -> DIN1_NUM_R {
50 DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8)
51 }
52 #[doc = "Bits 4:5 - SPI_WP input delay number."]
53 #[inline(always)]
54 pub fn din2_num(&self) -> DIN2_NUM_R {
55 DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8)
56 }
57 #[doc = "Bits 6:7 - SPI_HD input delay number."]
58 #[inline(always)]
59 pub fn din3_num(&self) -> DIN3_NUM_R {
60 DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8)
61 }
62 #[doc = "Bits 8:9 - SPI_IO4 input delay number."]
63 #[inline(always)]
64 pub fn din4_num(&self) -> DIN4_NUM_R {
65 DIN4_NUM_R::new(((self.bits >> 8) & 3) as u8)
66 }
67 #[doc = "Bits 10:11 - SPI_IO5 input delay number."]
68 #[inline(always)]
69 pub fn din5_num(&self) -> DIN5_NUM_R {
70 DIN5_NUM_R::new(((self.bits >> 10) & 3) as u8)
71 }
72 #[doc = "Bits 12:13 - SPI_IO6 input delay number."]
73 #[inline(always)]
74 pub fn din6_num(&self) -> DIN6_NUM_R {
75 DIN6_NUM_R::new(((self.bits >> 12) & 3) as u8)
76 }
77 #[doc = "Bits 14:15 - SPI_IO7 input delay number."]
78 #[inline(always)]
79 pub fn din7_num(&self) -> DIN7_NUM_R {
80 DIN7_NUM_R::new(((self.bits >> 14) & 3) as u8)
81 }
82 #[doc = "Bits 16:17 - SPI_DQS input delay number."]
83 #[inline(always)]
84 pub fn dins_num(&self) -> DINS_NUM_R {
85 DINS_NUM_R::new(((self.bits >> 16) & 3) as u8)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("DIN_NUM")
92 .field("din0_num", &self.din0_num())
93 .field("din1_num", &self.din1_num())
94 .field("din2_num", &self.din2_num())
95 .field("din3_num", &self.din3_num())
96 .field("din4_num", &self.din4_num())
97 .field("din5_num", &self.din5_num())
98 .field("din6_num", &self.din6_num())
99 .field("din7_num", &self.din7_num())
100 .field("dins_num", &self.dins_num())
101 .finish()
102 }
103}
104impl W {
105 #[doc = "Bits 0:1 - SPI_D input delay number."]
106 #[inline(always)]
107 pub fn din0_num(&mut self) -> DIN0_NUM_W<DIN_NUM_SPEC> {
108 DIN0_NUM_W::new(self, 0)
109 }
110 #[doc = "Bits 2:3 - SPI_Q input delay number."]
111 #[inline(always)]
112 pub fn din1_num(&mut self) -> DIN1_NUM_W<DIN_NUM_SPEC> {
113 DIN1_NUM_W::new(self, 2)
114 }
115 #[doc = "Bits 4:5 - SPI_WP input delay number."]
116 #[inline(always)]
117 pub fn din2_num(&mut self) -> DIN2_NUM_W<DIN_NUM_SPEC> {
118 DIN2_NUM_W::new(self, 4)
119 }
120 #[doc = "Bits 6:7 - SPI_HD input delay number."]
121 #[inline(always)]
122 pub fn din3_num(&mut self) -> DIN3_NUM_W<DIN_NUM_SPEC> {
123 DIN3_NUM_W::new(self, 6)
124 }
125 #[doc = "Bits 8:9 - SPI_IO4 input delay number."]
126 #[inline(always)]
127 pub fn din4_num(&mut self) -> DIN4_NUM_W<DIN_NUM_SPEC> {
128 DIN4_NUM_W::new(self, 8)
129 }
130 #[doc = "Bits 10:11 - SPI_IO5 input delay number."]
131 #[inline(always)]
132 pub fn din5_num(&mut self) -> DIN5_NUM_W<DIN_NUM_SPEC> {
133 DIN5_NUM_W::new(self, 10)
134 }
135 #[doc = "Bits 12:13 - SPI_IO6 input delay number."]
136 #[inline(always)]
137 pub fn din6_num(&mut self) -> DIN6_NUM_W<DIN_NUM_SPEC> {
138 DIN6_NUM_W::new(self, 12)
139 }
140 #[doc = "Bits 14:15 - SPI_IO7 input delay number."]
141 #[inline(always)]
142 pub fn din7_num(&mut self) -> DIN7_NUM_W<DIN_NUM_SPEC> {
143 DIN7_NUM_W::new(self, 14)
144 }
145 #[doc = "Bits 16:17 - SPI_DQS input delay number."]
146 #[inline(always)]
147 pub fn dins_num(&mut self) -> DINS_NUM_W<DIN_NUM_SPEC> {
148 DINS_NUM_W::new(self, 16)
149 }
150}
151#[doc = "MSPI input timing delay number control register when accesses to flash.\n\nYou can [`read`](crate::Reg::read) this register and get [`din_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`din_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct DIN_NUM_SPEC;
153impl crate::RegisterSpec for DIN_NUM_SPEC {
154 type Ux = u32;
155}
156#[doc = "`read()` method returns [`din_num::R`](R) reader structure"]
157impl crate::Readable for DIN_NUM_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`din_num::W`](W) writer structure"]
159impl crate::Writable for DIN_NUM_SPEC {
160 type Safety = crate::Unsafe;
161}
162#[doc = "`reset()` method sets DIN_NUM to value 0"]
163impl crate::Resettable for DIN_NUM_SPEC {}