esp32s3/spi0/
date.rs

1#[doc = "Register `DATE` reader"]
2pub type R = crate::R<DATE_SPEC>;
3#[doc = "Register `DATE` writer"]
4pub type W = crate::W<DATE_SPEC>;
5#[doc = "Field `SPI_SMEM_SPICLK_FUN_DRV` reader - The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM."]
6pub type SPI_SMEM_SPICLK_FUN_DRV_R = crate::FieldReader;
7#[doc = "Field `SPI_SMEM_SPICLK_FUN_DRV` writer - The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM."]
8pub type SPI_SMEM_SPICLK_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `SPI_FMEM_SPICLK_FUN_DRV` reader - The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash."]
10pub type SPI_FMEM_SPICLK_FUN_DRV_R = crate::FieldReader;
11#[doc = "Field `SPI_FMEM_SPICLK_FUN_DRV` writer - The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash."]
12pub type SPI_FMEM_SPICLK_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `SPI_SPICLK_PAD_DRV_CTL_EN` reader - SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] and SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV\\[1:0\\] of SPICLK PAD."]
14pub type SPI_SPICLK_PAD_DRV_CTL_EN_R = crate::BitReader;
15#[doc = "Field `SPI_SPICLK_PAD_DRV_CTL_EN` writer - SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] and SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV\\[1:0\\] of SPICLK PAD."]
16pub type SPI_SPICLK_PAD_DRV_CTL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DATE` reader - SPI register version."]
18pub type DATE_R = crate::FieldReader<u32>;
19#[doc = "Field `DATE` writer - SPI register version."]
20pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
21impl R {
22    #[doc = "Bits 0:1 - The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM."]
23    #[inline(always)]
24    pub fn spi_smem_spiclk_fun_drv(&self) -> SPI_SMEM_SPICLK_FUN_DRV_R {
25        SPI_SMEM_SPICLK_FUN_DRV_R::new((self.bits & 3) as u8)
26    }
27    #[doc = "Bits 2:3 - The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash."]
28    #[inline(always)]
29    pub fn spi_fmem_spiclk_fun_drv(&self) -> SPI_FMEM_SPICLK_FUN_DRV_R {
30        SPI_FMEM_SPICLK_FUN_DRV_R::new(((self.bits >> 2) & 3) as u8)
31    }
32    #[doc = "Bit 4 - SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] and SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV\\[1:0\\] of SPICLK PAD."]
33    #[inline(always)]
34    pub fn spi_spiclk_pad_drv_ctl_en(&self) -> SPI_SPICLK_PAD_DRV_CTL_EN_R {
35        SPI_SPICLK_PAD_DRV_CTL_EN_R::new(((self.bits >> 4) & 1) != 0)
36    }
37    #[doc = "Bits 5:27 - SPI register version."]
38    #[inline(always)]
39    pub fn date(&self) -> DATE_R {
40        DATE_R::new((self.bits >> 5) & 0x007f_ffff)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("DATE")
47            .field("spi_smem_spiclk_fun_drv", &self.spi_smem_spiclk_fun_drv())
48            .field("spi_fmem_spiclk_fun_drv", &self.spi_fmem_spiclk_fun_drv())
49            .field(
50                "spi_spiclk_pad_drv_ctl_en",
51                &self.spi_spiclk_pad_drv_ctl_en(),
52            )
53            .field("date", &self.date())
54            .finish()
55    }
56}
57impl W {
58    #[doc = "Bits 0:1 - The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM."]
59    #[inline(always)]
60    pub fn spi_smem_spiclk_fun_drv(&mut self) -> SPI_SMEM_SPICLK_FUN_DRV_W<DATE_SPEC> {
61        SPI_SMEM_SPICLK_FUN_DRV_W::new(self, 0)
62    }
63    #[doc = "Bits 2:3 - The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash."]
64    #[inline(always)]
65    pub fn spi_fmem_spiclk_fun_drv(&mut self) -> SPI_FMEM_SPICLK_FUN_DRV_W<DATE_SPEC> {
66        SPI_FMEM_SPICLK_FUN_DRV_W::new(self, 2)
67    }
68    #[doc = "Bit 4 - SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV\\[1:0\\] and SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV\\[1:0\\] of SPICLK PAD."]
69    #[inline(always)]
70    pub fn spi_spiclk_pad_drv_ctl_en(&mut self) -> SPI_SPICLK_PAD_DRV_CTL_EN_W<DATE_SPEC> {
71        SPI_SPICLK_PAD_DRV_CTL_EN_W::new(self, 4)
72    }
73    #[doc = "Bits 5:27 - SPI register version."]
74    #[inline(always)]
75    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
76        DATE_W::new(self, 5)
77    }
78}
79#[doc = "SPI0 version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct DATE_SPEC;
81impl crate::RegisterSpec for DATE_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`date::R`](R) reader structure"]
85impl crate::Readable for DATE_SPEC {}
86#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
87impl crate::Writable for DATE_SPEC {
88    type Safety = crate::Unsafe;
89}
90#[doc = "`reset()` method sets DATE to value 0x0210_1040"]
91impl crate::Resettable for DATE_SPEC {
92    const RESET_VALUE: u32 = 0x0210_1040;
93}
esp32s3/spi0/date.rs

esp32s3/spi0/
date.rs
