esp32s3/sens/
sar_cocpu_state.rs

1#[doc = "Register `SAR_COCPU_STATE` reader"]
2pub type R = crate::R<SAR_COCPU_STATE_SPEC>;
3#[doc = "Register `SAR_COCPU_STATE` writer"]
4pub type W = crate::W<SAR_COCPU_STATE_SPEC>;
5#[doc = "Field `SAR_COCPU_DBG_TRIGGER` writer - trigger cocpu debug registers"]
6pub type SAR_COCPU_DBG_TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `SAR_COCPU_CLK_EN_ST` reader - check cocpu whether clk on"]
8pub type SAR_COCPU_CLK_EN_ST_R = crate::BitReader;
9#[doc = "Field `SAR_COCPU_RESET_N` reader - check cocpu whether in reset state"]
10pub type SAR_COCPU_RESET_N_R = crate::BitReader;
11#[doc = "Field `SAR_COCPU_EOI` reader - check cocpu whether in interrupt state"]
12pub type SAR_COCPU_EOI_R = crate::BitReader;
13#[doc = "Field `SAR_COCPU_TRAP` reader - check cocpu whether in trap state"]
14pub type SAR_COCPU_TRAP_R = crate::BitReader;
15#[doc = "Field `SAR_COCPU_EBREAK` reader - check cocpu whether in ebreak"]
16pub type SAR_COCPU_EBREAK_R = crate::BitReader;
17impl R {
18    #[doc = "Bit 26 - check cocpu whether clk on"]
19    #[inline(always)]
20    pub fn sar_cocpu_clk_en_st(&self) -> SAR_COCPU_CLK_EN_ST_R {
21        SAR_COCPU_CLK_EN_ST_R::new(((self.bits >> 26) & 1) != 0)
22    }
23    #[doc = "Bit 27 - check cocpu whether in reset state"]
24    #[inline(always)]
25    pub fn sar_cocpu_reset_n(&self) -> SAR_COCPU_RESET_N_R {
26        SAR_COCPU_RESET_N_R::new(((self.bits >> 27) & 1) != 0)
27    }
28    #[doc = "Bit 28 - check cocpu whether in interrupt state"]
29    #[inline(always)]
30    pub fn sar_cocpu_eoi(&self) -> SAR_COCPU_EOI_R {
31        SAR_COCPU_EOI_R::new(((self.bits >> 28) & 1) != 0)
32    }
33    #[doc = "Bit 29 - check cocpu whether in trap state"]
34    #[inline(always)]
35    pub fn sar_cocpu_trap(&self) -> SAR_COCPU_TRAP_R {
36        SAR_COCPU_TRAP_R::new(((self.bits >> 29) & 1) != 0)
37    }
38    #[doc = "Bit 30 - check cocpu whether in ebreak"]
39    #[inline(always)]
40    pub fn sar_cocpu_ebreak(&self) -> SAR_COCPU_EBREAK_R {
41        SAR_COCPU_EBREAK_R::new(((self.bits >> 30) & 1) != 0)
42    }
43}
44#[cfg(feature = "impl-register-debug")]
45impl core::fmt::Debug for R {
46    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
47        f.debug_struct("SAR_COCPU_STATE")
48            .field("sar_cocpu_clk_en_st", &self.sar_cocpu_clk_en_st())
49            .field("sar_cocpu_reset_n", &self.sar_cocpu_reset_n())
50            .field("sar_cocpu_eoi", &self.sar_cocpu_eoi())
51            .field("sar_cocpu_trap", &self.sar_cocpu_trap())
52            .field("sar_cocpu_ebreak", &self.sar_cocpu_ebreak())
53            .finish()
54    }
55}
56impl W {
57    #[doc = "Bit 25 - trigger cocpu debug registers"]
58    #[inline(always)]
59    pub fn sar_cocpu_dbg_trigger(&mut self) -> SAR_COCPU_DBG_TRIGGER_W<SAR_COCPU_STATE_SPEC> {
60        SAR_COCPU_DBG_TRIGGER_W::new(self, 25)
61    }
62}
63#[doc = "get cocpu status\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
64pub struct SAR_COCPU_STATE_SPEC;
65impl crate::RegisterSpec for SAR_COCPU_STATE_SPEC {
66    type Ux = u32;
67}
68#[doc = "`read()` method returns [`sar_cocpu_state::R`](R) reader structure"]
69impl crate::Readable for SAR_COCPU_STATE_SPEC {}
70#[doc = "`write(|w| ..)` method takes [`sar_cocpu_state::W`](W) writer structure"]
71impl crate::Writable for SAR_COCPU_STATE_SPEC {
72    type Safety = crate::Unsafe;
73}
74#[doc = "`reset()` method sets SAR_COCPU_STATE to value 0"]
75impl crate::Resettable for SAR_COCPU_STATE_SPEC {}
esp32s3/sens/sar_cocpu_state.rs

esp32s3/sens/
sar_cocpu_state.rs
