esp32s3/i2s1/
rx_clkm_conf.rs

1#[doc = "Register `RX_CLKM_CONF` reader"]
2pub type R = crate::R<RX_CLKM_CONF_SPEC>;
3#[doc = "Register `RX_CLKM_CONF` writer"]
4pub type W = crate::W<RX_CLKM_CONF_SPEC>;
5#[doc = "Field `RX_CLKM_DIV_NUM` reader - Integral I2S clock divider value"]
6pub type RX_CLKM_DIV_NUM_R = crate::FieldReader;
7#[doc = "Field `RX_CLKM_DIV_NUM` writer - Integral I2S clock divider value"]
8pub type RX_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `RX_CLK_ACTIVE` reader - I2S Rx module clock enable signal."]
10pub type RX_CLK_ACTIVE_R = crate::BitReader;
11#[doc = "Field `RX_CLK_ACTIVE` writer - I2S Rx module clock enable signal."]
12pub type RX_CLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RX_CLK_SEL` reader - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
14pub type RX_CLK_SEL_R = crate::FieldReader;
15#[doc = "Field `RX_CLK_SEL` writer - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
16pub type RX_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `MCLK_SEL` reader - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
18pub type MCLK_SEL_R = crate::BitReader;
19#[doc = "Field `MCLK_SEL` writer - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
20pub type MCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:7 - Integral I2S clock divider value"]
23    #[inline(always)]
24    pub fn rx_clkm_div_num(&self) -> RX_CLKM_DIV_NUM_R {
25        RX_CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bit 26 - I2S Rx module clock enable signal."]
28    #[inline(always)]
29    pub fn rx_clk_active(&self) -> RX_CLK_ACTIVE_R {
30        RX_CLK_ACTIVE_R::new(((self.bits >> 26) & 1) != 0)
31    }
32    #[doc = "Bits 27:28 - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
33    #[inline(always)]
34    pub fn rx_clk_sel(&self) -> RX_CLK_SEL_R {
35        RX_CLK_SEL_R::new(((self.bits >> 27) & 3) as u8)
36    }
37    #[doc = "Bit 29 - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
38    #[inline(always)]
39    pub fn mclk_sel(&self) -> MCLK_SEL_R {
40        MCLK_SEL_R::new(((self.bits >> 29) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("RX_CLKM_CONF")
47            .field("rx_clkm_div_num", &self.rx_clkm_div_num())
48            .field("rx_clk_active", &self.rx_clk_active())
49            .field("rx_clk_sel", &self.rx_clk_sel())
50            .field("mclk_sel", &self.mclk_sel())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:7 - Integral I2S clock divider value"]
56    #[inline(always)]
57    pub fn rx_clkm_div_num(&mut self) -> RX_CLKM_DIV_NUM_W<RX_CLKM_CONF_SPEC> {
58        RX_CLKM_DIV_NUM_W::new(self, 0)
59    }
60    #[doc = "Bit 26 - I2S Rx module clock enable signal."]
61    #[inline(always)]
62    pub fn rx_clk_active(&mut self) -> RX_CLK_ACTIVE_W<RX_CLKM_CONF_SPEC> {
63        RX_CLK_ACTIVE_W::new(self, 26)
64    }
65    #[doc = "Bits 27:28 - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
66    #[inline(always)]
67    pub fn rx_clk_sel(&mut self) -> RX_CLK_SEL_W<RX_CLKM_CONF_SPEC> {
68        RX_CLK_SEL_W::new(self, 27)
69    }
70    #[doc = "Bit 29 - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
71    #[inline(always)]
72    pub fn mclk_sel(&mut self) -> MCLK_SEL_W<RX_CLKM_CONF_SPEC> {
73        MCLK_SEL_W::new(self, 29)
74    }
75}
76#[doc = "I2S RX clock configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_clkm_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_clkm_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct RX_CLKM_CONF_SPEC;
78impl crate::RegisterSpec for RX_CLKM_CONF_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`rx_clkm_conf::R`](R) reader structure"]
82impl crate::Readable for RX_CLKM_CONF_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`rx_clkm_conf::W`](W) writer structure"]
84impl crate::Writable for RX_CLKM_CONF_SPEC {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets RX_CLKM_CONF to value 0x02"]
88impl crate::Resettable for RX_CLKM_CONF_SPEC {
89    const RESET_VALUE: u32 = 0x02;
90}
esp32s3/i2s1/rx_clkm_conf.rs

esp32s3/i2s1/
rx_clkm_conf.rs
