esp32s3/extmem/
icache_prelock_sct_size.rs

1#[doc = "Register `ICACHE_PRELOCK_SCT_SIZE` reader"]
2pub type R = crate::R<ICACHE_PRELOCK_SCT_SIZE_SPEC>;
3#[doc = "Register `ICACHE_PRELOCK_SCT_SIZE` writer"]
4pub type W = crate::W<ICACHE_PRELOCK_SCT_SIZE_SPEC>;
5#[doc = "Field `ICACHE_PRELOCK_SCT1_SIZE` reader - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
6pub type ICACHE_PRELOCK_SCT1_SIZE_R = crate::FieldReader<u16>;
7#[doc = "Field `ICACHE_PRELOCK_SCT1_SIZE` writer - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
8pub type ICACHE_PRELOCK_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `ICACHE_PRELOCK_SCT0_SIZE` reader - The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG"]
10pub type ICACHE_PRELOCK_SCT0_SIZE_R = crate::FieldReader<u16>;
11#[doc = "Field `ICACHE_PRELOCK_SCT0_SIZE` writer - The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG"]
12pub type ICACHE_PRELOCK_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13impl R {
14    #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
15    #[inline(always)]
16    pub fn icache_prelock_sct1_size(&self) -> ICACHE_PRELOCK_SCT1_SIZE_R {
17        ICACHE_PRELOCK_SCT1_SIZE_R::new((self.bits & 0xffff) as u16)
18    }
19    #[doc = "Bits 16:31 - The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG"]
20    #[inline(always)]
21    pub fn icache_prelock_sct0_size(&self) -> ICACHE_PRELOCK_SCT0_SIZE_R {
22        ICACHE_PRELOCK_SCT0_SIZE_R::new(((self.bits >> 16) & 0xffff) as u16)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("ICACHE_PRELOCK_SCT_SIZE")
29            .field("icache_prelock_sct1_size", &self.icache_prelock_sct1_size())
30            .field("icache_prelock_sct0_size", &self.icache_prelock_sct0_size())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
36    #[inline(always)]
37    pub fn icache_prelock_sct1_size(
38        &mut self,
39    ) -> ICACHE_PRELOCK_SCT1_SIZE_W<ICACHE_PRELOCK_SCT_SIZE_SPEC> {
40        ICACHE_PRELOCK_SCT1_SIZE_W::new(self, 0)
41    }
42    #[doc = "Bits 16:31 - The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG"]
43    #[inline(always)]
44    pub fn icache_prelock_sct0_size(
45        &mut self,
46    ) -> ICACHE_PRELOCK_SCT0_SIZE_W<ICACHE_PRELOCK_SCT_SIZE_SPEC> {
47        ICACHE_PRELOCK_SCT0_SIZE_W::new(self, 16)
48    }
49}
50#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_prelock_sct_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_prelock_sct_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
51pub struct ICACHE_PRELOCK_SCT_SIZE_SPEC;
52impl crate::RegisterSpec for ICACHE_PRELOCK_SCT_SIZE_SPEC {
53    type Ux = u32;
54}
55#[doc = "`read()` method returns [`icache_prelock_sct_size::R`](R) reader structure"]
56impl crate::Readable for ICACHE_PRELOCK_SCT_SIZE_SPEC {}
57#[doc = "`write(|w| ..)` method takes [`icache_prelock_sct_size::W`](W) writer structure"]
58impl crate::Writable for ICACHE_PRELOCK_SCT_SIZE_SPEC {
59    type Safety = crate::Unsafe;
60}
61#[doc = "`reset()` method sets ICACHE_PRELOCK_SCT_SIZE to value 0"]
62impl crate::Resettable for ICACHE_PRELOCK_SCT_SIZE_SPEC {}
esp32s3/extmem/icache_prelock_sct_size.rs

esp32s3/extmem/
icache_prelock_sct_size.rs
