esp32s3/dma/ch/in_int/
ena.rs

1#[doc = "Register `ENA` reader"]
2pub type R = crate::R<ENA_SPEC>;
3#[doc = "Register `ENA` writer"]
4pub type W = crate::W<ENA_SPEC>;
5#[doc = "Field `IN_DONE` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
6pub type IN_DONE_R = crate::BitReader;
7#[doc = "Field `IN_DONE` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
8pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_SUC_EOF` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
10pub type IN_SUC_EOF_R = crate::BitReader;
11#[doc = "Field `IN_SUC_EOF` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
12pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `IN_ERR_EOF` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
14pub type IN_ERR_EOF_R = crate::BitReader;
15#[doc = "Field `IN_ERR_EOF` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
16pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IN_DSCR_ERR` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
18pub type IN_DSCR_ERR_R = crate::BitReader;
19#[doc = "Field `IN_DSCR_ERR` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
20pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `IN_DSCR_EMPTY` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
22pub type IN_DSCR_EMPTY_R = crate::BitReader;
23#[doc = "Field `IN_DSCR_EMPTY` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
24pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `INFIFO_FULL_WM` reader - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."]
26pub type INFIFO_FULL_WM_R = crate::BitReader;
27#[doc = "Field `INFIFO_FULL_WM` writer - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."]
28pub type INFIFO_FULL_WM_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `INFIFO_OVF_L1` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
30pub type INFIFO_OVF_L1_R = crate::BitReader;
31#[doc = "Field `INFIFO_OVF_L1` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
32pub type INFIFO_OVF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `INFIFO_UDF_L1` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
34pub type INFIFO_UDF_L1_R = crate::BitReader;
35#[doc = "Field `INFIFO_UDF_L1` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
36pub type INFIFO_UDF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `INFIFO_OVF_L3` reader - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."]
38pub type INFIFO_OVF_L3_R = crate::BitReader;
39#[doc = "Field `INFIFO_OVF_L3` writer - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."]
40pub type INFIFO_OVF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `INFIFO_UDF_L3` reader - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."]
42pub type INFIFO_UDF_L3_R = crate::BitReader;
43#[doc = "Field `INFIFO_UDF_L3` writer - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."]
44pub type INFIFO_UDF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
47    #[inline(always)]
48    pub fn in_done(&self) -> IN_DONE_R {
49        IN_DONE_R::new((self.bits & 1) != 0)
50    }
51    #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
52    #[inline(always)]
53    pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
54        IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0)
55    }
56    #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
57    #[inline(always)]
58    pub fn in_err_eof(&self) -> IN_ERR_EOF_R {
59        IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
62    #[inline(always)]
63    pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R {
64        IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0)
65    }
66    #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
67    #[inline(always)]
68    pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R {
69        IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
70    }
71    #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."]
72    #[inline(always)]
73    pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R {
74        INFIFO_FULL_WM_R::new(((self.bits >> 5) & 1) != 0)
75    }
76    #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
77    #[inline(always)]
78    pub fn infifo_ovf_l1(&self) -> INFIFO_OVF_L1_R {
79        INFIFO_OVF_L1_R::new(((self.bits >> 6) & 1) != 0)
80    }
81    #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
82    #[inline(always)]
83    pub fn infifo_udf_l1(&self) -> INFIFO_UDF_L1_R {
84        INFIFO_UDF_L1_R::new(((self.bits >> 7) & 1) != 0)
85    }
86    #[doc = "Bit 8 - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."]
87    #[inline(always)]
88    pub fn infifo_ovf_l3(&self) -> INFIFO_OVF_L3_R {
89        INFIFO_OVF_L3_R::new(((self.bits >> 8) & 1) != 0)
90    }
91    #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."]
92    #[inline(always)]
93    pub fn infifo_udf_l3(&self) -> INFIFO_UDF_L3_R {
94        INFIFO_UDF_L3_R::new(((self.bits >> 9) & 1) != 0)
95    }
96}
97#[cfg(feature = "impl-register-debug")]
98impl core::fmt::Debug for R {
99    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100        f.debug_struct("ENA")
101            .field("in_done", &self.in_done())
102            .field("in_suc_eof", &self.in_suc_eof())
103            .field("in_err_eof", &self.in_err_eof())
104            .field("in_dscr_err", &self.in_dscr_err())
105            .field("in_dscr_empty", &self.in_dscr_empty())
106            .field("infifo_full_wm", &self.infifo_full_wm())
107            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
108            .field("infifo_udf_l1", &self.infifo_udf_l1())
109            .field("infifo_ovf_l3", &self.infifo_ovf_l3())
110            .field("infifo_udf_l3", &self.infifo_udf_l3())
111            .finish()
112    }
113}
114impl W {
115    #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
116    #[inline(always)]
117    pub fn in_done(&mut self) -> IN_DONE_W<ENA_SPEC> {
118        IN_DONE_W::new(self, 0)
119    }
120    #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
121    #[inline(always)]
122    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<ENA_SPEC> {
123        IN_SUC_EOF_W::new(self, 1)
124    }
125    #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
126    #[inline(always)]
127    pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<ENA_SPEC> {
128        IN_ERR_EOF_W::new(self, 2)
129    }
130    #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
131    #[inline(always)]
132    pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<ENA_SPEC> {
133        IN_DSCR_ERR_W::new(self, 3)
134    }
135    #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
136    #[inline(always)]
137    pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<ENA_SPEC> {
138        IN_DSCR_EMPTY_W::new(self, 4)
139    }
140    #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."]
141    #[inline(always)]
142    pub fn infifo_full_wm(&mut self) -> INFIFO_FULL_WM_W<ENA_SPEC> {
143        INFIFO_FULL_WM_W::new(self, 5)
144    }
145    #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
146    #[inline(always)]
147    pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<ENA_SPEC> {
148        INFIFO_OVF_L1_W::new(self, 6)
149    }
150    #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
151    #[inline(always)]
152    pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<ENA_SPEC> {
153        INFIFO_UDF_L1_W::new(self, 7)
154    }
155    #[doc = "Bit 8 - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."]
156    #[inline(always)]
157    pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<ENA_SPEC> {
158        INFIFO_OVF_L3_W::new(self, 8)
159    }
160    #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."]
161    #[inline(always)]
162    pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<ENA_SPEC> {
163        INFIFO_UDF_L3_W::new(self, 9)
164    }
165}
166#[doc = "Interrupt enable bits of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct ENA_SPEC;
168impl crate::RegisterSpec for ENA_SPEC {
169    type Ux = u32;
170}
171#[doc = "`read()` method returns [`ena::R`](R) reader structure"]
172impl crate::Readable for ENA_SPEC {}
173#[doc = "`write(|w| ..)` method takes [`ena::W`](W) writer structure"]
174impl crate::Writable for ENA_SPEC {
175    type Safety = crate::Unsafe;
176}
177#[doc = "`reset()` method sets ENA to value 0"]
178impl crate::Resettable for ENA_SPEC {}
esp32s3/dma/ch/in_int/ena.rs

esp32s3/dma/ch/in_int/
ena.rs
