Module lcd_dly_mode

LCD signal delay configuration register

Structs

LCD_DLY_MODE_SPEC

LCD signal delay configuration register

Type Aliases

LCD_CD_MODE_R

Field LCD_CD_MODE reader - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.

LCD_CD_MODE_W

Field LCD_CD_MODE writer - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.

LCD_DE_MODE_R

Field LCD_DE_MODE reader - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.

LCD_DE_MODE_W

Field LCD_DE_MODE writer - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.

LCD_HSYNC_MODE_R

Field LCD_HSYNC_MODE reader - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.

LCD_HSYNC_MODE_W

Field LCD_HSYNC_MODE writer - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.

LCD_VSYNC_MODE_R

Field LCD_VSYNC_MODE reader - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delay by the falling edge of LCD_CLK.

LCD_VSYNC_MODE_W

Field LCD_VSYNC_MODE writer - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delay by the falling edge of LCD_CLK.

R

Register LCD_DLY_MODE reader

W

Register LCD_DLY_MODE writer