Expand description
SPI misc register
Structs§
- MISC_
SPEC - SPI misc register
Type Aliases§
- ADDR_
DTR_ EN_ R - Field
ADDR_DTR_EN
reader - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. - ADDR_
DTR_ EN_ W - Field
ADDR_DTR_EN
writer - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. - CK_
DIS_ R - Field
CK_DIS
reader - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. - CK_
DIS_ W - Field
CK_DIS
writer - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. - CK_
IDLE_ EDGE_ R - Field
CK_IDLE_EDGE
reader - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. - CK_
IDLE_ EDGE_ W - Field
CK_IDLE_EDGE
writer - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. - CLK_
DATA_ DTR_ EN_ R - Field
CLK_DATA_DTR_EN
reader - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. - CLK_
DATA_ DTR_ EN_ W - Field
CLK_DATA_DTR_EN
writer - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. - CMD_
DTR_ EN_ R - Field
CMD_DTR_EN
reader - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. - CMD_
DTR_ EN_ W - Field
CMD_DTR_EN
writer - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. - CS0_
DIS_ R - Field
CS0_DIS
reader - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. - CS0_
DIS_ W - Field
CS0_DIS
writer - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. - CS1_
DIS_ R - Field
CS1_DIS
reader - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. - CS1_
DIS_ W - Field
CS1_DIS
writer - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. - CS2_
DIS_ R - Field
CS2_DIS
reader - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. - CS2_
DIS_ W - Field
CS2_DIS
writer - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. - CS3_
DIS_ R - Field
CS3_DIS
reader - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. - CS3_
DIS_ W - Field
CS3_DIS
writer - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. - CS4_
DIS_ R - Field
CS4_DIS
reader - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. - CS4_
DIS_ W - Field
CS4_DIS
writer - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. - CS5_
DIS_ R - Field
CS5_DIS
reader - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. - CS5_
DIS_ W - Field
CS5_DIS
writer - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. - CS_
KEEP_ ACTIVE_ R - Field
CS_KEEP_ACTIVE
reader - spi cs line keep low when the bit is set. Can be configured in CONF state. - CS_
KEEP_ ACTIVE_ W - Field
CS_KEEP_ACTIVE
writer - spi cs line keep low when the bit is set. Can be configured in CONF state. - DATA_
DTR_ EN_ R - Field
DATA_DTR_EN
reader - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. - DATA_
DTR_ EN_ W - Field
DATA_DTR_EN
writer - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. - DQS_
IDLE_ EDGE_ R - Field
DQS_IDLE_EDGE
reader - The default value of spi_dqs. Can be configured in CONF state. - DQS_
IDLE_ EDGE_ W - Field
DQS_IDLE_EDGE
writer - The default value of spi_dqs. Can be configured in CONF state. - MASTER_
CS_ POL_ R - Field
MASTER_CS_POL
reader - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. - MASTER_
CS_ POL_ W - Field
MASTER_CS_POL
writer - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. - QUAD_
DIN_ PIN_ SWAP_ R - Field
QUAD_DIN_PIN_SWAP
reader - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. - QUAD_
DIN_ PIN_ SWAP_ W - Field
QUAD_DIN_PIN_SWAP
writer - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. - R
- Register
MISC
reader - SLAVE_
CS_ POL_ R - Field
SLAVE_CS_POL
reader - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. - SLAVE_
CS_ POL_ W - Field
SLAVE_CS_POL
writer - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. - W
- Register
MISC
writer