Expand description
SPI0 external RAM mode control register
Structs§
- SRAM_
CMD_ SPEC - SPI0 external RAM mode control register
Type Aliases§
- R
- Register
SRAM_CMD
reader - SADDR_
DUAL_ R - Field
SADDR_DUAL
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase. - SADDR_
DUAL_ W - Field
SADDR_DUAL
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase. - SADDR_
OCT_ R - Field
SADDR_OCT
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase. - SADDR_
OCT_ W - Field
SADDR_OCT
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase. - SADDR_
QUAD_ R - Field
SADDR_QUAD
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase. - SADDR_
QUAD_ W - Field
SADDR_QUAD
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase. - SCLK_
MODE_ R - Field
SCLK_MODE
reader - SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on. - SCLK_
MODE_ W - Field
SCLK_MODE
writer - SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on. - SCMD_
DUAL_ R - Field
SCMD_DUAL
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase. - SCMD_
DUAL_ W - Field
SCMD_DUAL
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase. - SCMD_
OCT_ R - Field
SCMD_OCT
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase. - SCMD_
OCT_ W - Field
SCMD_OCT
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase. - SCMD_
QUAD_ R - Field
SCMD_QUAD
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase. - SCMD_
QUAD_ W - Field
SCMD_QUAD
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase. - SDIN_
DUAL_ R - Field
SDIN_DUAL
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase. - SDIN_
DUAL_ W - Field
SDIN_DUAL
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase. - SDIN_
OCT_ R - Field
SDIN_OCT
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase. - SDIN_
OCT_ W - Field
SDIN_OCT
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase. - SDIN_
QUAD_ R - Field
SDIN_QUAD
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase. - SDIN_
QUAD_ W - Field
SDIN_QUAD
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase. - SDOUT_
DUAL_ R - Field
SDOUT_DUAL
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase. - SDOUT_
DUAL_ W - Field
SDOUT_DUAL
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase. - SDOUT_
OCT_ R - Field
SDOUT_OCT
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase. - SDOUT_
OCT_ W - Field
SDOUT_OCT
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase. - SDOUT_
QUAD_ R - Field
SDOUT_QUAD
reader - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase. - SDOUT_
QUAD_ W - Field
SDOUT_QUAD
writer - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase. - SDUMMY_
OUT_ R - Field
SDUMMY_OUT
reader - When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. - SDUMMY_
OUT_ W - Field
SDUMMY_OUT
writer - When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. - SWB_
MODE_ R - Field
SWB_MODE
reader - Mode bits when SPI0 accesses to Ext_RAM. - SWB_
MODE_ W - Field
SWB_MODE
writer - Mode bits when SPI0 accesses to Ext_RAM. - W
- Register
SRAM_CMD
writer