Expand description
Control register
Structs§
- CTRL_
SPEC - Control register
Type Aliases§
- ABORT_
READ_ DATA_ R - Field
ABORT_READ_DATA
reader - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. - ABORT_
READ_ DATA_ W - Field
ABORT_READ_DATA
writer - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. - CEATA_
DEVICE_ INTERRUPT_ STATUS_ R - Field
CEATA_DEVICE_INTERRUPT_STATUS
reader - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device’s interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device’s interrupt, then software should set this bit. - CEATA_
DEVICE_ INTERRUPT_ STATUS_ W - Field
CEATA_DEVICE_INTERRUPT_STATUS
writer - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device’s interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device’s interrupt, then software should set this bit. - CONTROLLER_
RESET_ R - Field
CONTROLLER_RESET
reader - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. - CONTROLLER_
RESET_ W - Field
CONTROLLER_RESET
writer - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. - DMA_
RESET_ R - Field
DMA_RESET
reader - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. - DMA_
RESET_ W - Field
DMA_RESET
writer - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. - FIFO_
RESET_ R - Field
FIFO_RESET
reader - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. - FIFO_
RESET_ W - Field
FIFO_RESET
writer - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. - INT_
ENABLE_ R - Field
INT_ENABLE
reader - Global interrupt enable/disable bit. 0: Disable; 1: Enable. - INT_
ENABLE_ W - Field
INT_ENABLE
writer - Global interrupt enable/disable bit. 0: Disable; 1: Enable. - R
- Register
CTRL
reader - READ_
WAIT_ R - Field
READ_WAIT
reader - For sending read-wait to SDIO cards. - READ_
WAIT_ W - Field
READ_WAIT
writer - For sending read-wait to SDIO cards. - SEND_
AUTO_ STOP_ CCSD_ R - Field
SEND_AUTO_STOP_CCSD
reader - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. - SEND_
AUTO_ STOP_ CCSD_ W - Field
SEND_AUTO_STOP_CCSD
writer - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. - SEND_
CCSD_ R - Field
SEND_CCSD
reader - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. - SEND_
CCSD_ W - Field
SEND_CCSD
writer - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. - SEND_
IRQ_ RESPONSE_ R - Field
SEND_IRQ_RESPONSE
reader - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. - SEND_
IRQ_ RESPONSE_ W - Field
SEND_IRQ_RESPONSE
writer - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. - W
- Register
CTRL
writer