esp32s3/system/
bt_lpck_div_frac.rs

1#[doc = "Register `BT_LPCK_DIV_FRAC` reader"]
2pub type R = crate::R<BT_LPCK_DIV_FRAC_SPEC>;
3#[doc = "Register `BT_LPCK_DIV_FRAC` writer"]
4pub type W = crate::W<BT_LPCK_DIV_FRAC_SPEC>;
5#[doc = "Field `BT_LPCK_DIV_B` reader - This field is lower power clock frequent division factor b"]
6pub type BT_LPCK_DIV_B_R = crate::FieldReader<u16>;
7#[doc = "Field `BT_LPCK_DIV_B` writer - This field is lower power clock frequent division factor b"]
8pub type BT_LPCK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Field `BT_LPCK_DIV_A` reader - This field is lower power clock frequent division factor a"]
10pub type BT_LPCK_DIV_A_R = crate::FieldReader<u16>;
11#[doc = "Field `BT_LPCK_DIV_A` writer - This field is lower power clock frequent division factor a"]
12pub type BT_LPCK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
13#[doc = "Field `LPCLK_SEL_RTC_SLOW` reader - Set 1 to select rtc-slow clock as rtc low power clock"]
14pub type LPCLK_SEL_RTC_SLOW_R = crate::BitReader;
15#[doc = "Field `LPCLK_SEL_RTC_SLOW` writer - Set 1 to select rtc-slow clock as rtc low power clock"]
16pub type LPCLK_SEL_RTC_SLOW_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `LPCLK_SEL_8M` reader - Set 1 to select 8m clock as rtc low power clock"]
18pub type LPCLK_SEL_8M_R = crate::BitReader;
19#[doc = "Field `LPCLK_SEL_8M` writer - Set 1 to select 8m clock as rtc low power clock"]
20pub type LPCLK_SEL_8M_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `LPCLK_SEL_XTAL` reader - Set 1 to select xtal clock as rtc low power clock"]
22pub type LPCLK_SEL_XTAL_R = crate::BitReader;
23#[doc = "Field `LPCLK_SEL_XTAL` writer - Set 1 to select xtal clock as rtc low power clock"]
24pub type LPCLK_SEL_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `LPCLK_SEL_XTAL32K` reader - Set 1 to select xtal32k clock as low power clock"]
26pub type LPCLK_SEL_XTAL32K_R = crate::BitReader;
27#[doc = "Field `LPCLK_SEL_XTAL32K` writer - Set 1 to select xtal32k clock as low power clock"]
28pub type LPCLK_SEL_XTAL32K_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `LPCLK_RTC_EN` reader - Set 1 to enable RTC low power clock"]
30pub type LPCLK_RTC_EN_R = crate::BitReader;
31#[doc = "Field `LPCLK_RTC_EN` writer - Set 1 to enable RTC low power clock"]
32pub type LPCLK_RTC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bits 0:11 - This field is lower power clock frequent division factor b"]
35    #[inline(always)]
36    pub fn bt_lpck_div_b(&self) -> BT_LPCK_DIV_B_R {
37        BT_LPCK_DIV_B_R::new((self.bits & 0x0fff) as u16)
38    }
39    #[doc = "Bits 12:23 - This field is lower power clock frequent division factor a"]
40    #[inline(always)]
41    pub fn bt_lpck_div_a(&self) -> BT_LPCK_DIV_A_R {
42        BT_LPCK_DIV_A_R::new(((self.bits >> 12) & 0x0fff) as u16)
43    }
44    #[doc = "Bit 24 - Set 1 to select rtc-slow clock as rtc low power clock"]
45    #[inline(always)]
46    pub fn lpclk_sel_rtc_slow(&self) -> LPCLK_SEL_RTC_SLOW_R {
47        LPCLK_SEL_RTC_SLOW_R::new(((self.bits >> 24) & 1) != 0)
48    }
49    #[doc = "Bit 25 - Set 1 to select 8m clock as rtc low power clock"]
50    #[inline(always)]
51    pub fn lpclk_sel_8m(&self) -> LPCLK_SEL_8M_R {
52        LPCLK_SEL_8M_R::new(((self.bits >> 25) & 1) != 0)
53    }
54    #[doc = "Bit 26 - Set 1 to select xtal clock as rtc low power clock"]
55    #[inline(always)]
56    pub fn lpclk_sel_xtal(&self) -> LPCLK_SEL_XTAL_R {
57        LPCLK_SEL_XTAL_R::new(((self.bits >> 26) & 1) != 0)
58    }
59    #[doc = "Bit 27 - Set 1 to select xtal32k clock as low power clock"]
60    #[inline(always)]
61    pub fn lpclk_sel_xtal32k(&self) -> LPCLK_SEL_XTAL32K_R {
62        LPCLK_SEL_XTAL32K_R::new(((self.bits >> 27) & 1) != 0)
63    }
64    #[doc = "Bit 28 - Set 1 to enable RTC low power clock"]
65    #[inline(always)]
66    pub fn lpclk_rtc_en(&self) -> LPCLK_RTC_EN_R {
67        LPCLK_RTC_EN_R::new(((self.bits >> 28) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("BT_LPCK_DIV_FRAC")
74            .field("bt_lpck_div_b", &self.bt_lpck_div_b())
75            .field("bt_lpck_div_a", &self.bt_lpck_div_a())
76            .field("lpclk_sel_rtc_slow", &self.lpclk_sel_rtc_slow())
77            .field("lpclk_sel_8m", &self.lpclk_sel_8m())
78            .field("lpclk_sel_xtal", &self.lpclk_sel_xtal())
79            .field("lpclk_sel_xtal32k", &self.lpclk_sel_xtal32k())
80            .field("lpclk_rtc_en", &self.lpclk_rtc_en())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bits 0:11 - This field is lower power clock frequent division factor b"]
86    #[inline(always)]
87    pub fn bt_lpck_div_b(&mut self) -> BT_LPCK_DIV_B_W<BT_LPCK_DIV_FRAC_SPEC> {
88        BT_LPCK_DIV_B_W::new(self, 0)
89    }
90    #[doc = "Bits 12:23 - This field is lower power clock frequent division factor a"]
91    #[inline(always)]
92    pub fn bt_lpck_div_a(&mut self) -> BT_LPCK_DIV_A_W<BT_LPCK_DIV_FRAC_SPEC> {
93        BT_LPCK_DIV_A_W::new(self, 12)
94    }
95    #[doc = "Bit 24 - Set 1 to select rtc-slow clock as rtc low power clock"]
96    #[inline(always)]
97    pub fn lpclk_sel_rtc_slow(&mut self) -> LPCLK_SEL_RTC_SLOW_W<BT_LPCK_DIV_FRAC_SPEC> {
98        LPCLK_SEL_RTC_SLOW_W::new(self, 24)
99    }
100    #[doc = "Bit 25 - Set 1 to select 8m clock as rtc low power clock"]
101    #[inline(always)]
102    pub fn lpclk_sel_8m(&mut self) -> LPCLK_SEL_8M_W<BT_LPCK_DIV_FRAC_SPEC> {
103        LPCLK_SEL_8M_W::new(self, 25)
104    }
105    #[doc = "Bit 26 - Set 1 to select xtal clock as rtc low power clock"]
106    #[inline(always)]
107    pub fn lpclk_sel_xtal(&mut self) -> LPCLK_SEL_XTAL_W<BT_LPCK_DIV_FRAC_SPEC> {
108        LPCLK_SEL_XTAL_W::new(self, 26)
109    }
110    #[doc = "Bit 27 - Set 1 to select xtal32k clock as low power clock"]
111    #[inline(always)]
112    pub fn lpclk_sel_xtal32k(&mut self) -> LPCLK_SEL_XTAL32K_W<BT_LPCK_DIV_FRAC_SPEC> {
113        LPCLK_SEL_XTAL32K_W::new(self, 27)
114    }
115    #[doc = "Bit 28 - Set 1 to enable RTC low power clock"]
116    #[inline(always)]
117    pub fn lpclk_rtc_en(&mut self) -> LPCLK_RTC_EN_W<BT_LPCK_DIV_FRAC_SPEC> {
118        LPCLK_RTC_EN_W::new(self, 28)
119    }
120}
121#[doc = "low power clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`bt_lpck_div_frac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bt_lpck_div_frac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct BT_LPCK_DIV_FRAC_SPEC;
123impl crate::RegisterSpec for BT_LPCK_DIV_FRAC_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`bt_lpck_div_frac::R`](R) reader structure"]
127impl crate::Readable for BT_LPCK_DIV_FRAC_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`bt_lpck_div_frac::W`](W) writer structure"]
129impl crate::Writable for BT_LPCK_DIV_FRAC_SPEC {
130    type Safety = crate::Unsafe;
131    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets BT_LPCK_DIV_FRAC to value 0x0200_1001"]
135impl crate::Resettable for BT_LPCK_DIV_FRAC_SPEC {
136    const RESET_VALUE: u32 = 0x0200_1001;
137}
esp32s3/system/bt_lpck_div_frac.rs

esp32s3/system/
bt_lpck_div_frac.rs
