esp32s3/uart0/
mem_conf.rs

1#[doc = "Register `MEM_CONF` reader"]
2pub type R = crate::R<MEM_CONF_SPEC>;
3#[doc = "Register `MEM_CONF` writer"]
4pub type W = crate::W<MEM_CONF_SPEC>;
5#[doc = "Field `RX_SIZE` reader - This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes."]
6pub type RX_SIZE_R = crate::FieldReader;
7#[doc = "Field `RX_SIZE` writer - This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes."]
8pub type RX_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `TX_SIZE` reader - This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes."]
10pub type TX_SIZE_R = crate::FieldReader;
11#[doc = "Field `TX_SIZE` writer - This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes."]
12pub type TX_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `RX_FLOW_THRHD` reader - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
14pub type RX_FLOW_THRHD_R = crate::FieldReader<u16>;
15#[doc = "Field `RX_FLOW_THRHD` writer - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
16pub type RX_FLOW_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
17#[doc = "Field `RX_TOUT_THRHD` reader - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."]
18pub type RX_TOUT_THRHD_R = crate::FieldReader<u16>;
19#[doc = "Field `RX_TOUT_THRHD` writer - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."]
20pub type RX_TOUT_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
21#[doc = "Field `MEM_FORCE_PD` reader - Set this bit to force power down UART memory."]
22pub type MEM_FORCE_PD_R = crate::BitReader;
23#[doc = "Field `MEM_FORCE_PD` writer - Set this bit to force power down UART memory."]
24pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `MEM_FORCE_PU` reader - Set this bit to force power up UART memory."]
26pub type MEM_FORCE_PU_R = crate::BitReader;
27#[doc = "Field `MEM_FORCE_PU` writer - Set this bit to force power up UART memory."]
28pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bits 1:3 - This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes."]
31    #[inline(always)]
32    pub fn rx_size(&self) -> RX_SIZE_R {
33        RX_SIZE_R::new(((self.bits >> 1) & 7) as u8)
34    }
35    #[doc = "Bits 4:6 - This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes."]
36    #[inline(always)]
37    pub fn tx_size(&self) -> TX_SIZE_R {
38        TX_SIZE_R::new(((self.bits >> 4) & 7) as u8)
39    }
40    #[doc = "Bits 7:16 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
41    #[inline(always)]
42    pub fn rx_flow_thrhd(&self) -> RX_FLOW_THRHD_R {
43        RX_FLOW_THRHD_R::new(((self.bits >> 7) & 0x03ff) as u16)
44    }
45    #[doc = "Bits 17:26 - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."]
46    #[inline(always)]
47    pub fn rx_tout_thrhd(&self) -> RX_TOUT_THRHD_R {
48        RX_TOUT_THRHD_R::new(((self.bits >> 17) & 0x03ff) as u16)
49    }
50    #[doc = "Bit 27 - Set this bit to force power down UART memory."]
51    #[inline(always)]
52    pub fn mem_force_pd(&self) -> MEM_FORCE_PD_R {
53        MEM_FORCE_PD_R::new(((self.bits >> 27) & 1) != 0)
54    }
55    #[doc = "Bit 28 - Set this bit to force power up UART memory."]
56    #[inline(always)]
57    pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R {
58        MEM_FORCE_PU_R::new(((self.bits >> 28) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("MEM_CONF")
65            .field("rx_size", &self.rx_size())
66            .field("tx_size", &self.tx_size())
67            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
68            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
69            .field("mem_force_pd", &self.mem_force_pd())
70            .field("mem_force_pu", &self.mem_force_pu())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bits 1:3 - This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes."]
76    #[inline(always)]
77    pub fn rx_size(&mut self) -> RX_SIZE_W<MEM_CONF_SPEC> {
78        RX_SIZE_W::new(self, 1)
79    }
80    #[doc = "Bits 4:6 - This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes."]
81    #[inline(always)]
82    pub fn tx_size(&mut self) -> TX_SIZE_W<MEM_CONF_SPEC> {
83        TX_SIZE_W::new(self, 4)
84    }
85    #[doc = "Bits 7:16 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
86    #[inline(always)]
87    pub fn rx_flow_thrhd(&mut self) -> RX_FLOW_THRHD_W<MEM_CONF_SPEC> {
88        RX_FLOW_THRHD_W::new(self, 7)
89    }
90    #[doc = "Bits 17:26 - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."]
91    #[inline(always)]
92    pub fn rx_tout_thrhd(&mut self) -> RX_TOUT_THRHD_W<MEM_CONF_SPEC> {
93        RX_TOUT_THRHD_W::new(self, 17)
94    }
95    #[doc = "Bit 27 - Set this bit to force power down UART memory."]
96    #[inline(always)]
97    pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W<MEM_CONF_SPEC> {
98        MEM_FORCE_PD_W::new(self, 27)
99    }
100    #[doc = "Bit 28 - Set this bit to force power up UART memory."]
101    #[inline(always)]
102    pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W<MEM_CONF_SPEC> {
103        MEM_FORCE_PU_W::new(self, 28)
104    }
105}
106#[doc = "UART threshold and allocation configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct MEM_CONF_SPEC;
108impl crate::RegisterSpec for MEM_CONF_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`mem_conf::R`](R) reader structure"]
112impl crate::Readable for MEM_CONF_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`mem_conf::W`](W) writer structure"]
114impl crate::Writable for MEM_CONF_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets MEM_CONF to value 0x0014_0012"]
120impl crate::Resettable for MEM_CONF_SPEC {
121    const RESET_VALUE: u32 = 0x0014_0012;
122}
esp32s3/uart0/mem_conf.rs

esp32s3/uart0/
mem_conf.rs
