esp32s3/spi1/
flash_sus_cmd.rs

1#[doc = "Register `FLASH_SUS_CMD` reader"]
2pub type R = crate::R<FLASH_SUS_CMD_SPEC>;
3#[doc = "Register `FLASH_SUS_CMD` writer"]
4pub type W = crate::W<FLASH_SUS_CMD_SPEC>;
5#[doc = "Field `FLASH_PER` reader - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
6pub type FLASH_PER_R = crate::BitReader;
7#[doc = "Field `FLASH_PER` writer - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
8pub type FLASH_PER_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FLASH_PES` reader - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
10pub type FLASH_PES_R = crate::BitReader;
11#[doc = "Field `FLASH_PES` writer - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
12pub type FLASH_PES_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FLASH_PER_WAIT_EN` reader - Set this bit to add delay time after program erase resume(PER) is sent."]
14pub type FLASH_PER_WAIT_EN_R = crate::BitReader;
15#[doc = "Field `FLASH_PER_WAIT_EN` writer - Set this bit to add delay time after program erase resume(PER) is sent."]
16pub type FLASH_PER_WAIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FLASH_PES_WAIT_EN` reader - Set this bit to add delay time after program erase suspend(PES) command is sent."]
18pub type FLASH_PES_WAIT_EN_R = crate::BitReader;
19#[doc = "Field `FLASH_PES_WAIT_EN` writer - Set this bit to add delay time after program erase suspend(PES) command is sent."]
20pub type FLASH_PES_WAIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PES_PER_EN` reader - Set this bit to enable PES transfer trigger PES transfer option."]
22pub type PES_PER_EN_R = crate::BitReader;
23#[doc = "Field `PES_PER_EN` writer - Set this bit to enable PES transfer trigger PES transfer option."]
24pub type PES_PER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PESR_IDLE_EN` reader - 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate."]
26pub type PESR_IDLE_EN_R = crate::BitReader;
27#[doc = "Field `PESR_IDLE_EN` writer - 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate."]
28pub type PESR_IDLE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
31    #[inline(always)]
32    pub fn flash_per(&self) -> FLASH_PER_R {
33        FLASH_PER_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
36    #[inline(always)]
37    pub fn flash_pes(&self) -> FLASH_PES_R {
38        FLASH_PES_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - Set this bit to add delay time after program erase resume(PER) is sent."]
41    #[inline(always)]
42    pub fn flash_per_wait_en(&self) -> FLASH_PER_WAIT_EN_R {
43        FLASH_PER_WAIT_EN_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - Set this bit to add delay time after program erase suspend(PES) command is sent."]
46    #[inline(always)]
47    pub fn flash_pes_wait_en(&self) -> FLASH_PES_WAIT_EN_R {
48        FLASH_PES_WAIT_EN_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - Set this bit to enable PES transfer trigger PES transfer option."]
51    #[inline(always)]
52    pub fn pes_per_en(&self) -> PES_PER_EN_R {
53        PES_PER_EN_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate."]
56    #[inline(always)]
57    pub fn pesr_idle_en(&self) -> PESR_IDLE_EN_R {
58        PESR_IDLE_EN_R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("FLASH_SUS_CMD")
65            .field("flash_per", &self.flash_per())
66            .field("flash_pes", &self.flash_pes())
67            .field("flash_per_wait_en", &self.flash_per_wait_en())
68            .field("flash_pes_wait_en", &self.flash_pes_wait_en())
69            .field("pes_per_en", &self.pes_per_en())
70            .field("pesr_idle_en", &self.pesr_idle_en())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
76    #[inline(always)]
77    pub fn flash_per(&mut self) -> FLASH_PER_W<FLASH_SUS_CMD_SPEC> {
78        FLASH_PER_W::new(self, 0)
79    }
80    #[doc = "Bit 1 - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
81    #[inline(always)]
82    pub fn flash_pes(&mut self) -> FLASH_PES_W<FLASH_SUS_CMD_SPEC> {
83        FLASH_PES_W::new(self, 1)
84    }
85    #[doc = "Bit 2 - Set this bit to add delay time after program erase resume(PER) is sent."]
86    #[inline(always)]
87    pub fn flash_per_wait_en(&mut self) -> FLASH_PER_WAIT_EN_W<FLASH_SUS_CMD_SPEC> {
88        FLASH_PER_WAIT_EN_W::new(self, 2)
89    }
90    #[doc = "Bit 3 - Set this bit to add delay time after program erase suspend(PES) command is sent."]
91    #[inline(always)]
92    pub fn flash_pes_wait_en(&mut self) -> FLASH_PES_WAIT_EN_W<FLASH_SUS_CMD_SPEC> {
93        FLASH_PES_WAIT_EN_W::new(self, 3)
94    }
95    #[doc = "Bit 4 - Set this bit to enable PES transfer trigger PES transfer option."]
96    #[inline(always)]
97    pub fn pes_per_en(&mut self) -> PES_PER_EN_W<FLASH_SUS_CMD_SPEC> {
98        PES_PER_EN_W::new(self, 4)
99    }
100    #[doc = "Bit 5 - 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate."]
101    #[inline(always)]
102    pub fn pesr_idle_en(&mut self) -> PESR_IDLE_EN_W<FLASH_SUS_CMD_SPEC> {
103        PESR_IDLE_EN_W::new(self, 5)
104    }
105}
106#[doc = "SPI1 flash suspend control register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_sus_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_sus_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct FLASH_SUS_CMD_SPEC;
108impl crate::RegisterSpec for FLASH_SUS_CMD_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`flash_sus_cmd::R`](R) reader structure"]
112impl crate::Readable for FLASH_SUS_CMD_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`flash_sus_cmd::W`](W) writer structure"]
114impl crate::Writable for FLASH_SUS_CMD_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets FLASH_SUS_CMD to value 0"]
120impl crate::Resettable for FLASH_SUS_CMD_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
esp32s3/spi1/flash_sus_cmd.rs

esp32s3/spi1/
flash_sus_cmd.rs
