esp32s3/rtc_cntl/
timer1.rs

1#[doc = "Register `TIMER1` reader"]
2pub type R = crate::R<TIMER1_SPEC>;
3#[doc = "Register `TIMER1` writer"]
4pub type W = crate::W<TIMER1_SPEC>;
5#[doc = "Field `CPU_STALL_EN` reader - CPU stall enable bit"]
6pub type CPU_STALL_EN_R = crate::BitReader;
7#[doc = "Field `CPU_STALL_EN` writer - CPU stall enable bit"]
8pub type CPU_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CPU_STALL_WAIT` reader - CPU stall wait cycles in fast_clk_rtc"]
10pub type CPU_STALL_WAIT_R = crate::FieldReader;
11#[doc = "Field `CPU_STALL_WAIT` writer - CPU stall wait cycles in fast_clk_rtc"]
12pub type CPU_STALL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `CK8M_WAIT` reader - CK8M wait cycles in slow_clk_rtc"]
14pub type CK8M_WAIT_R = crate::FieldReader;
15#[doc = "Field `CK8M_WAIT` writer - CK8M wait cycles in slow_clk_rtc"]
16pub type CK8M_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `XTL_BUF_WAIT` reader - XTAL wait cycles in slow_clk_rtc"]
18pub type XTL_BUF_WAIT_R = crate::FieldReader<u16>;
19#[doc = "Field `XTL_BUF_WAIT` writer - XTAL wait cycles in slow_clk_rtc"]
20pub type XTL_BUF_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
21#[doc = "Field `PLL_BUF_WAIT` reader - PLL wait cycles in slow_clk_rtc"]
22pub type PLL_BUF_WAIT_R = crate::FieldReader;
23#[doc = "Field `PLL_BUF_WAIT` writer - PLL wait cycles in slow_clk_rtc"]
24pub type PLL_BUF_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25impl R {
26    #[doc = "Bit 0 - CPU stall enable bit"]
27    #[inline(always)]
28    pub fn cpu_stall_en(&self) -> CPU_STALL_EN_R {
29        CPU_STALL_EN_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bits 1:5 - CPU stall wait cycles in fast_clk_rtc"]
32    #[inline(always)]
33    pub fn cpu_stall_wait(&self) -> CPU_STALL_WAIT_R {
34        CPU_STALL_WAIT_R::new(((self.bits >> 1) & 0x1f) as u8)
35    }
36    #[doc = "Bits 6:13 - CK8M wait cycles in slow_clk_rtc"]
37    #[inline(always)]
38    pub fn ck8m_wait(&self) -> CK8M_WAIT_R {
39        CK8M_WAIT_R::new(((self.bits >> 6) & 0xff) as u8)
40    }
41    #[doc = "Bits 14:23 - XTAL wait cycles in slow_clk_rtc"]
42    #[inline(always)]
43    pub fn xtl_buf_wait(&self) -> XTL_BUF_WAIT_R {
44        XTL_BUF_WAIT_R::new(((self.bits >> 14) & 0x03ff) as u16)
45    }
46    #[doc = "Bits 24:31 - PLL wait cycles in slow_clk_rtc"]
47    #[inline(always)]
48    pub fn pll_buf_wait(&self) -> PLL_BUF_WAIT_R {
49        PLL_BUF_WAIT_R::new(((self.bits >> 24) & 0xff) as u8)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("TIMER1")
56            .field("cpu_stall_en", &self.cpu_stall_en())
57            .field("cpu_stall_wait", &self.cpu_stall_wait())
58            .field("ck8m_wait", &self.ck8m_wait())
59            .field("xtl_buf_wait", &self.xtl_buf_wait())
60            .field("pll_buf_wait", &self.pll_buf_wait())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 0 - CPU stall enable bit"]
66    #[inline(always)]
67    pub fn cpu_stall_en(&mut self) -> CPU_STALL_EN_W<TIMER1_SPEC> {
68        CPU_STALL_EN_W::new(self, 0)
69    }
70    #[doc = "Bits 1:5 - CPU stall wait cycles in fast_clk_rtc"]
71    #[inline(always)]
72    pub fn cpu_stall_wait(&mut self) -> CPU_STALL_WAIT_W<TIMER1_SPEC> {
73        CPU_STALL_WAIT_W::new(self, 1)
74    }
75    #[doc = "Bits 6:13 - CK8M wait cycles in slow_clk_rtc"]
76    #[inline(always)]
77    pub fn ck8m_wait(&mut self) -> CK8M_WAIT_W<TIMER1_SPEC> {
78        CK8M_WAIT_W::new(self, 6)
79    }
80    #[doc = "Bits 14:23 - XTAL wait cycles in slow_clk_rtc"]
81    #[inline(always)]
82    pub fn xtl_buf_wait(&mut self) -> XTL_BUF_WAIT_W<TIMER1_SPEC> {
83        XTL_BUF_WAIT_W::new(self, 14)
84    }
85    #[doc = "Bits 24:31 - PLL wait cycles in slow_clk_rtc"]
86    #[inline(always)]
87    pub fn pll_buf_wait(&mut self) -> PLL_BUF_WAIT_W<TIMER1_SPEC> {
88        PLL_BUF_WAIT_W::new(self, 24)
89    }
90}
91#[doc = "rtc state wait time\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct TIMER1_SPEC;
93impl crate::RegisterSpec for TIMER1_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`timer1::R`](R) reader structure"]
97impl crate::Readable for TIMER1_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`timer1::W`](W) writer structure"]
99impl crate::Writable for TIMER1_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets TIMER1 to value 0x2814_0403"]
105impl crate::Resettable for TIMER1_SPEC {
106    const RESET_VALUE: u32 = 0x2814_0403;
107}
esp32s3/rtc_cntl/timer1.rs

esp32s3/rtc_cntl/
timer1.rs
