esp32s3/rtc_cntl/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `SLP_WAKEUP` writer - Clear sleep wakeup interrupt state"]
4pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `SLP_REJECT` writer - Clear sleep reject interrupt state"]
6pub type SLP_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `SDIO_IDLE` writer - Clear SDIO idle interrupt state"]
8pub type SDIO_IDLE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `WDT` writer - Clear RTC WDT interrupt state"]
10pub type WDT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `TOUCH_SCAN_DONE` writer - clear touch scan done interrupt raw"]
12pub type TOUCH_SCAN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ULP_CP` writer - Clear ULP-coprocessor interrupt state"]
14pub type ULP_CP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `TOUCH_DONE` writer - Clear touch done interrupt state"]
16pub type TOUCH_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TOUCH_ACTIVE` writer - Clear touch active interrupt state"]
18pub type TOUCH_ACTIVE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `TOUCH_INACTIVE` writer - Clear touch inactive interrupt state"]
20pub type TOUCH_INACTIVE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `BROWN_OUT` writer - Clear brown out interrupt state"]
22pub type BROWN_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `MAIN_TIMER` writer - Clear RTC main timer interrupt state"]
24pub type MAIN_TIMER_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `SARADC1` writer - Clear saradc1 interrupt state"]
26pub type SARADC1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `TSENS` writer - Clear tsens interrupt state"]
28pub type TSENS_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `COCPU` writer - Clear riscV cocpu interrupt state"]
30pub type COCPU_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SARADC2` writer - Clear saradc2 interrupt state"]
32pub type SARADC2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `SWD` writer - Clear super watch dog interrupt state"]
34pub type SWD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `XTAL32K_DEAD` writer - Clear RTC WDT interrupt state"]
36pub type XTAL32K_DEAD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `COCPU_TRAP` writer - Clear cocpu trap interrupt state"]
38pub type COCPU_TRAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `TOUCH_TIMEOUT` writer - Clear touch timeout interrupt state"]
40pub type TOUCH_TIMEOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `GLITCH_DET` writer - Clear glitch det interrupt state"]
42pub type GLITCH_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
43#[doc = "Field `TOUCH_APPROACH_LOOP_DONE` writer - cleartouch approach mode loop interrupt state"]
44pub type TOUCH_APPROACH_LOOP_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
45#[cfg(feature = "impl-register-debug")]
46impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
47    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
48        write!(f, "(not readable)")
49    }
50}
51impl W {
52    #[doc = "Bit 0 - Clear sleep wakeup interrupt state"]
53    #[inline(always)]
54    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_CLR_SPEC> {
55        SLP_WAKEUP_W::new(self, 0)
56    }
57    #[doc = "Bit 1 - Clear sleep reject interrupt state"]
58    #[inline(always)]
59    pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_CLR_SPEC> {
60        SLP_REJECT_W::new(self, 1)
61    }
62    #[doc = "Bit 2 - Clear SDIO idle interrupt state"]
63    #[inline(always)]
64    pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_CLR_SPEC> {
65        SDIO_IDLE_W::new(self, 2)
66    }
67    #[doc = "Bit 3 - Clear RTC WDT interrupt state"]
68    #[inline(always)]
69    pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
70        WDT_W::new(self, 3)
71    }
72    #[doc = "Bit 4 - clear touch scan done interrupt raw"]
73    #[inline(always)]
74    pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_CLR_SPEC> {
75        TOUCH_SCAN_DONE_W::new(self, 4)
76    }
77    #[doc = "Bit 5 - Clear ULP-coprocessor interrupt state"]
78    #[inline(always)]
79    pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_CLR_SPEC> {
80        ULP_CP_W::new(self, 5)
81    }
82    #[doc = "Bit 6 - Clear touch done interrupt state"]
83    #[inline(always)]
84    pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_CLR_SPEC> {
85        TOUCH_DONE_W::new(self, 6)
86    }
87    #[doc = "Bit 7 - Clear touch active interrupt state"]
88    #[inline(always)]
89    pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_CLR_SPEC> {
90        TOUCH_ACTIVE_W::new(self, 7)
91    }
92    #[doc = "Bit 8 - Clear touch inactive interrupt state"]
93    #[inline(always)]
94    pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_CLR_SPEC> {
95        TOUCH_INACTIVE_W::new(self, 8)
96    }
97    #[doc = "Bit 9 - Clear brown out interrupt state"]
98    #[inline(always)]
99    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
100        BROWN_OUT_W::new(self, 9)
101    }
102    #[doc = "Bit 10 - Clear RTC main timer interrupt state"]
103    #[inline(always)]
104    pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_CLR_SPEC> {
105        MAIN_TIMER_W::new(self, 10)
106    }
107    #[doc = "Bit 11 - Clear saradc1 interrupt state"]
108    #[inline(always)]
109    pub fn saradc1(&mut self) -> SARADC1_W<INT_CLR_SPEC> {
110        SARADC1_W::new(self, 11)
111    }
112    #[doc = "Bit 12 - Clear tsens interrupt state"]
113    #[inline(always)]
114    pub fn tsens(&mut self) -> TSENS_W<INT_CLR_SPEC> {
115        TSENS_W::new(self, 12)
116    }
117    #[doc = "Bit 13 - Clear riscV cocpu interrupt state"]
118    #[inline(always)]
119    pub fn cocpu(&mut self) -> COCPU_W<INT_CLR_SPEC> {
120        COCPU_W::new(self, 13)
121    }
122    #[doc = "Bit 14 - Clear saradc2 interrupt state"]
123    #[inline(always)]
124    pub fn saradc2(&mut self) -> SARADC2_W<INT_CLR_SPEC> {
125        SARADC2_W::new(self, 14)
126    }
127    #[doc = "Bit 15 - Clear super watch dog interrupt state"]
128    #[inline(always)]
129    pub fn swd(&mut self) -> SWD_W<INT_CLR_SPEC> {
130        SWD_W::new(self, 15)
131    }
132    #[doc = "Bit 16 - Clear RTC WDT interrupt state"]
133    #[inline(always)]
134    pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_CLR_SPEC> {
135        XTAL32K_DEAD_W::new(self, 16)
136    }
137    #[doc = "Bit 17 - Clear cocpu trap interrupt state"]
138    #[inline(always)]
139    pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_CLR_SPEC> {
140        COCPU_TRAP_W::new(self, 17)
141    }
142    #[doc = "Bit 18 - Clear touch timeout interrupt state"]
143    #[inline(always)]
144    pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_CLR_SPEC> {
145        TOUCH_TIMEOUT_W::new(self, 18)
146    }
147    #[doc = "Bit 19 - Clear glitch det interrupt state"]
148    #[inline(always)]
149    pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
150        GLITCH_DET_W::new(self, 19)
151    }
152    #[doc = "Bit 20 - cleartouch approach mode loop interrupt state"]
153    #[inline(always)]
154    pub fn touch_approach_loop_done(&mut self) -> TOUCH_APPROACH_LOOP_DONE_W<INT_CLR_SPEC> {
155        TOUCH_APPROACH_LOOP_DONE_W::new(self, 20)
156    }
157}
158#[doc = "rtc interrupt register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
159pub struct INT_CLR_SPEC;
160impl crate::RegisterSpec for INT_CLR_SPEC {
161    type Ux = u32;
162}
163#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
164impl crate::Writable for INT_CLR_SPEC {
165    type Safety = crate::Unsafe;
166    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
167    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x001f_ffff;
168}
169#[doc = "`reset()` method sets INT_CLR to value 0"]
170impl crate::Resettable for INT_CLR_SPEC {
171    const RESET_VALUE: u32 = 0;
172}
esp32s3/rtc_cntl/int_clr.rs

esp32s3/rtc_cntl/
int_clr.rs
