esp32s3/mcpwm0/
fault_detect.rs

1#[doc = "Register `FAULT_DETECT` reader"]
2pub type R = crate::R<FAULT_DETECT_SPEC>;
3#[doc = "Register `FAULT_DETECT` writer"]
4pub type W = crate::W<FAULT_DETECT_SPEC>;
5#[doc = "Field `F0_EN` reader - When set, event_f0 generation is enabled"]
6pub type F0_EN_R = crate::BitReader;
7#[doc = "Field `F0_EN` writer - When set, event_f0 generation is enabled"]
8pub type F0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `F1_EN` reader - When set, event_f1 generation is enabled"]
10pub type F1_EN_R = crate::BitReader;
11#[doc = "Field `F1_EN` writer - When set, event_f1 generation is enabled"]
12pub type F1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `F2_EN` reader - When set, event_f2 generation is enabled"]
14pub type F2_EN_R = crate::BitReader;
15#[doc = "Field `F2_EN` writer - When set, event_f2 generation is enabled"]
16pub type F2_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `F0_POLE` reader - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
18pub type F0_POLE_R = crate::BitReader;
19#[doc = "Field `F0_POLE` writer - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
20pub type F0_POLE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `F1_POLE` reader - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
22pub type F1_POLE_R = crate::BitReader;
23#[doc = "Field `F1_POLE` writer - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
24pub type F1_POLE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `F2_POLE` reader - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
26pub type F2_POLE_R = crate::BitReader;
27#[doc = "Field `F2_POLE` writer - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
28pub type F2_POLE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `EVENT_F0` reader - Set and reset by hardware. If set, event_f0 is on going"]
30pub type EVENT_F0_R = crate::BitReader;
31#[doc = "Field `EVENT_F1` reader - Set and reset by hardware. If set, event_f1 is on going"]
32pub type EVENT_F1_R = crate::BitReader;
33#[doc = "Field `EVENT_F2` reader - Set and reset by hardware. If set, event_f2 is on going"]
34pub type EVENT_F2_R = crate::BitReader;
35impl R {
36    #[doc = "Bit 0 - When set, event_f0 generation is enabled"]
37    #[inline(always)]
38    pub fn f0_en(&self) -> F0_EN_R {
39        F0_EN_R::new((self.bits & 1) != 0)
40    }
41    #[doc = "Bit 1 - When set, event_f1 generation is enabled"]
42    #[inline(always)]
43    pub fn f1_en(&self) -> F1_EN_R {
44        F1_EN_R::new(((self.bits >> 1) & 1) != 0)
45    }
46    #[doc = "Bit 2 - When set, event_f2 generation is enabled"]
47    #[inline(always)]
48    pub fn f2_en(&self) -> F2_EN_R {
49        F2_EN_R::new(((self.bits >> 2) & 1) != 0)
50    }
51    #[doc = "Bit 3 - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
52    #[inline(always)]
53    pub fn f0_pole(&self) -> F0_POLE_R {
54        F0_POLE_R::new(((self.bits >> 3) & 1) != 0)
55    }
56    #[doc = "Bit 4 - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
57    #[inline(always)]
58    pub fn f1_pole(&self) -> F1_POLE_R {
59        F1_POLE_R::new(((self.bits >> 4) & 1) != 0)
60    }
61    #[doc = "Bit 5 - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
62    #[inline(always)]
63    pub fn f2_pole(&self) -> F2_POLE_R {
64        F2_POLE_R::new(((self.bits >> 5) & 1) != 0)
65    }
66    #[doc = "Bit 6 - Set and reset by hardware. If set, event_f0 is on going"]
67    #[inline(always)]
68    pub fn event_f0(&self) -> EVENT_F0_R {
69        EVENT_F0_R::new(((self.bits >> 6) & 1) != 0)
70    }
71    #[doc = "Bit 7 - Set and reset by hardware. If set, event_f1 is on going"]
72    #[inline(always)]
73    pub fn event_f1(&self) -> EVENT_F1_R {
74        EVENT_F1_R::new(((self.bits >> 7) & 1) != 0)
75    }
76    #[doc = "Bit 8 - Set and reset by hardware. If set, event_f2 is on going"]
77    #[inline(always)]
78    pub fn event_f2(&self) -> EVENT_F2_R {
79        EVENT_F2_R::new(((self.bits >> 8) & 1) != 0)
80    }
81}
82#[cfg(feature = "impl-register-debug")]
83impl core::fmt::Debug for R {
84    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
85        f.debug_struct("FAULT_DETECT")
86            .field("f0_en", &self.f0_en())
87            .field("f1_en", &self.f1_en())
88            .field("f2_en", &self.f2_en())
89            .field("f0_pole", &self.f0_pole())
90            .field("f1_pole", &self.f1_pole())
91            .field("f2_pole", &self.f2_pole())
92            .field("event_f0", &self.event_f0())
93            .field("event_f1", &self.event_f1())
94            .field("event_f2", &self.event_f2())
95            .finish()
96    }
97}
98impl W {
99    #[doc = "Bit 0 - When set, event_f0 generation is enabled"]
100    #[inline(always)]
101    pub fn f0_en(&mut self) -> F0_EN_W<FAULT_DETECT_SPEC> {
102        F0_EN_W::new(self, 0)
103    }
104    #[doc = "Bit 1 - When set, event_f1 generation is enabled"]
105    #[inline(always)]
106    pub fn f1_en(&mut self) -> F1_EN_W<FAULT_DETECT_SPEC> {
107        F1_EN_W::new(self, 1)
108    }
109    #[doc = "Bit 2 - When set, event_f2 generation is enabled"]
110    #[inline(always)]
111    pub fn f2_en(&mut self) -> F2_EN_W<FAULT_DETECT_SPEC> {
112        F2_EN_W::new(self, 2)
113    }
114    #[doc = "Bit 3 - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
115    #[inline(always)]
116    pub fn f0_pole(&mut self) -> F0_POLE_W<FAULT_DETECT_SPEC> {
117        F0_POLE_W::new(self, 3)
118    }
119    #[doc = "Bit 4 - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
120    #[inline(always)]
121    pub fn f1_pole(&mut self) -> F1_POLE_W<FAULT_DETECT_SPEC> {
122        F1_POLE_W::new(self, 4)
123    }
124    #[doc = "Bit 5 - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
125    #[inline(always)]
126    pub fn f2_pole(&mut self) -> F2_POLE_W<FAULT_DETECT_SPEC> {
127        F2_POLE_W::new(self, 5)
128    }
129}
130#[doc = "Fault detection configuration and status\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_detect::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_detect::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
131pub struct FAULT_DETECT_SPEC;
132impl crate::RegisterSpec for FAULT_DETECT_SPEC {
133    type Ux = u32;
134}
135#[doc = "`read()` method returns [`fault_detect::R`](R) reader structure"]
136impl crate::Readable for FAULT_DETECT_SPEC {}
137#[doc = "`write(|w| ..)` method takes [`fault_detect::W`](W) writer structure"]
138impl crate::Writable for FAULT_DETECT_SPEC {
139    type Safety = crate::Unsafe;
140    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
141    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
142}
143#[doc = "`reset()` method sets FAULT_DETECT to value 0"]
144impl crate::Resettable for FAULT_DETECT_SPEC {
145    const RESET_VALUE: u32 = 0;
146}
esp32s3/mcpwm0/fault_detect.rs

esp32s3/mcpwm0/
fault_detect.rs
