esp32s3/lcd_cam/
lcd_ctrl2.rs

1#[doc = "Register `LCD_CTRL2` reader"]
2pub type R = crate::R<LCD_CTRL2_SPEC>;
3#[doc = "Register `LCD_CTRL2` writer"]
4pub type W = crate::W<LCD_CTRL2_SPEC>;
5#[doc = "Field `LCD_VSYNC_WIDTH` reader - It is the width of LCD_VSYNC active pulse in a line."]
6pub type LCD_VSYNC_WIDTH_R = crate::FieldReader;
7#[doc = "Field `LCD_VSYNC_WIDTH` writer - It is the width of LCD_VSYNC active pulse in a line."]
8pub type LCD_VSYNC_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
9#[doc = "Field `LCD_VSYNC_IDLE_POL` reader - It is the idle value of LCD_VSYNC."]
10pub type LCD_VSYNC_IDLE_POL_R = crate::BitReader;
11#[doc = "Field `LCD_VSYNC_IDLE_POL` writer - It is the idle value of LCD_VSYNC."]
12pub type LCD_VSYNC_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `LCD_DE_IDLE_POL` reader - It is the idle value of LCD_DE."]
14pub type LCD_DE_IDLE_POL_R = crate::BitReader;
15#[doc = "Field `LCD_DE_IDLE_POL` writer - It is the idle value of LCD_DE."]
16pub type LCD_DE_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `LCD_HS_BLANK_EN` reader - 1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode."]
18pub type LCD_HS_BLANK_EN_R = crate::BitReader;
19#[doc = "Field `LCD_HS_BLANK_EN` writer - 1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode."]
20pub type LCD_HS_BLANK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `LCD_HSYNC_WIDTH` reader - It is the width of LCD_HSYNC active pulse in a line."]
22pub type LCD_HSYNC_WIDTH_R = crate::FieldReader;
23#[doc = "Field `LCD_HSYNC_WIDTH` writer - It is the width of LCD_HSYNC active pulse in a line."]
24pub type LCD_HSYNC_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
25#[doc = "Field `LCD_HSYNC_IDLE_POL` reader - It is the idle value of LCD_HSYNC."]
26pub type LCD_HSYNC_IDLE_POL_R = crate::BitReader;
27#[doc = "Field `LCD_HSYNC_IDLE_POL` writer - It is the idle value of LCD_HSYNC."]
28pub type LCD_HSYNC_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `LCD_HSYNC_POSITION` reader - It is the position of LCD_HSYNC active pulse in a line."]
30pub type LCD_HSYNC_POSITION_R = crate::FieldReader;
31#[doc = "Field `LCD_HSYNC_POSITION` writer - It is the position of LCD_HSYNC active pulse in a line."]
32pub type LCD_HSYNC_POSITION_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
33impl R {
34    #[doc = "Bits 0:6 - It is the width of LCD_VSYNC active pulse in a line."]
35    #[inline(always)]
36    pub fn lcd_vsync_width(&self) -> LCD_VSYNC_WIDTH_R {
37        LCD_VSYNC_WIDTH_R::new((self.bits & 0x7f) as u8)
38    }
39    #[doc = "Bit 7 - It is the idle value of LCD_VSYNC."]
40    #[inline(always)]
41    pub fn lcd_vsync_idle_pol(&self) -> LCD_VSYNC_IDLE_POL_R {
42        LCD_VSYNC_IDLE_POL_R::new(((self.bits >> 7) & 1) != 0)
43    }
44    #[doc = "Bit 8 - It is the idle value of LCD_DE."]
45    #[inline(always)]
46    pub fn lcd_de_idle_pol(&self) -> LCD_DE_IDLE_POL_R {
47        LCD_DE_IDLE_POL_R::new(((self.bits >> 8) & 1) != 0)
48    }
49    #[doc = "Bit 9 - 1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode."]
50    #[inline(always)]
51    pub fn lcd_hs_blank_en(&self) -> LCD_HS_BLANK_EN_R {
52        LCD_HS_BLANK_EN_R::new(((self.bits >> 9) & 1) != 0)
53    }
54    #[doc = "Bits 16:22 - It is the width of LCD_HSYNC active pulse in a line."]
55    #[inline(always)]
56    pub fn lcd_hsync_width(&self) -> LCD_HSYNC_WIDTH_R {
57        LCD_HSYNC_WIDTH_R::new(((self.bits >> 16) & 0x7f) as u8)
58    }
59    #[doc = "Bit 23 - It is the idle value of LCD_HSYNC."]
60    #[inline(always)]
61    pub fn lcd_hsync_idle_pol(&self) -> LCD_HSYNC_IDLE_POL_R {
62        LCD_HSYNC_IDLE_POL_R::new(((self.bits >> 23) & 1) != 0)
63    }
64    #[doc = "Bits 24:31 - It is the position of LCD_HSYNC active pulse in a line."]
65    #[inline(always)]
66    pub fn lcd_hsync_position(&self) -> LCD_HSYNC_POSITION_R {
67        LCD_HSYNC_POSITION_R::new(((self.bits >> 24) & 0xff) as u8)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("LCD_CTRL2")
74            .field("lcd_vsync_width", &self.lcd_vsync_width())
75            .field("lcd_vsync_idle_pol", &self.lcd_vsync_idle_pol())
76            .field("lcd_de_idle_pol", &self.lcd_de_idle_pol())
77            .field("lcd_hs_blank_en", &self.lcd_hs_blank_en())
78            .field("lcd_hsync_width", &self.lcd_hsync_width())
79            .field("lcd_hsync_idle_pol", &self.lcd_hsync_idle_pol())
80            .field("lcd_hsync_position", &self.lcd_hsync_position())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bits 0:6 - It is the width of LCD_VSYNC active pulse in a line."]
86    #[inline(always)]
87    pub fn lcd_vsync_width(&mut self) -> LCD_VSYNC_WIDTH_W<LCD_CTRL2_SPEC> {
88        LCD_VSYNC_WIDTH_W::new(self, 0)
89    }
90    #[doc = "Bit 7 - It is the idle value of LCD_VSYNC."]
91    #[inline(always)]
92    pub fn lcd_vsync_idle_pol(&mut self) -> LCD_VSYNC_IDLE_POL_W<LCD_CTRL2_SPEC> {
93        LCD_VSYNC_IDLE_POL_W::new(self, 7)
94    }
95    #[doc = "Bit 8 - It is the idle value of LCD_DE."]
96    #[inline(always)]
97    pub fn lcd_de_idle_pol(&mut self) -> LCD_DE_IDLE_POL_W<LCD_CTRL2_SPEC> {
98        LCD_DE_IDLE_POL_W::new(self, 8)
99    }
100    #[doc = "Bit 9 - 1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode."]
101    #[inline(always)]
102    pub fn lcd_hs_blank_en(&mut self) -> LCD_HS_BLANK_EN_W<LCD_CTRL2_SPEC> {
103        LCD_HS_BLANK_EN_W::new(self, 9)
104    }
105    #[doc = "Bits 16:22 - It is the width of LCD_HSYNC active pulse in a line."]
106    #[inline(always)]
107    pub fn lcd_hsync_width(&mut self) -> LCD_HSYNC_WIDTH_W<LCD_CTRL2_SPEC> {
108        LCD_HSYNC_WIDTH_W::new(self, 16)
109    }
110    #[doc = "Bit 23 - It is the idle value of LCD_HSYNC."]
111    #[inline(always)]
112    pub fn lcd_hsync_idle_pol(&mut self) -> LCD_HSYNC_IDLE_POL_W<LCD_CTRL2_SPEC> {
113        LCD_HSYNC_IDLE_POL_W::new(self, 23)
114    }
115    #[doc = "Bits 24:31 - It is the position of LCD_HSYNC active pulse in a line."]
116    #[inline(always)]
117    pub fn lcd_hsync_position(&mut self) -> LCD_HSYNC_POSITION_W<LCD_CTRL2_SPEC> {
118        LCD_HSYNC_POSITION_W::new(self, 24)
119    }
120}
121#[doc = "LCD signal configuration register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct LCD_CTRL2_SPEC;
123impl crate::RegisterSpec for LCD_CTRL2_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`lcd_ctrl2::R`](R) reader structure"]
127impl crate::Readable for LCD_CTRL2_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`lcd_ctrl2::W`](W) writer structure"]
129impl crate::Writable for LCD_CTRL2_SPEC {
130    type Safety = crate::Unsafe;
131    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets LCD_CTRL2 to value 0"]
135impl crate::Resettable for LCD_CTRL2_SPEC {
136    const RESET_VALUE: u32 = 0;
137}
esp32s3/lcd_cam/lcd_ctrl2.rs

esp32s3/lcd_cam/
lcd_ctrl2.rs
