esp32s3/extmem/
core1_acs_cache_int_st.rs

1#[doc = "Register `CORE1_ACS_CACHE_INT_ST` reader"]
2pub type R = crate::R<CORE1_ACS_CACHE_INT_ST_SPEC>;
3#[doc = "Field `CORE1_IBUS_ACS_MSK_ICACHE_ST` reader - The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access."]
4pub type CORE1_IBUS_ACS_MSK_ICACHE_ST_R = crate::BitReader;
5#[doc = "Field `CORE1_IBUS_WR_ICACHE_ST` reader - The bit is used to indicate interrupt by ibus trying to write icache"]
6pub type CORE1_IBUS_WR_ICACHE_ST_R = crate::BitReader;
7#[doc = "Field `CORE1_IBUS_REJECT_ST` reader - The bit is used to indicate interrupt by authentication fail."]
8pub type CORE1_IBUS_REJECT_ST_R = crate::BitReader;
9#[doc = "Field `CORE1_DBUS_ACS_MSK_DCACHE_ST` reader - The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access."]
10pub type CORE1_DBUS_ACS_MSK_DCACHE_ST_R = crate::BitReader;
11#[doc = "Field `CORE1_DBUS_REJECT_ST` reader - The bit is used to indicate interrupt by authentication fail."]
12pub type CORE1_DBUS_REJECT_ST_R = crate::BitReader;
13impl R {
14    #[doc = "Bit 0 - The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access."]
15    #[inline(always)]
16    pub fn core1_ibus_acs_msk_icache_st(&self) -> CORE1_IBUS_ACS_MSK_ICACHE_ST_R {
17        CORE1_IBUS_ACS_MSK_ICACHE_ST_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 1 - The bit is used to indicate interrupt by ibus trying to write icache"]
20    #[inline(always)]
21    pub fn core1_ibus_wr_icache_st(&self) -> CORE1_IBUS_WR_ICACHE_ST_R {
22        CORE1_IBUS_WR_ICACHE_ST_R::new(((self.bits >> 1) & 1) != 0)
23    }
24    #[doc = "Bit 2 - The bit is used to indicate interrupt by authentication fail."]
25    #[inline(always)]
26    pub fn core1_ibus_reject_st(&self) -> CORE1_IBUS_REJECT_ST_R {
27        CORE1_IBUS_REJECT_ST_R::new(((self.bits >> 2) & 1) != 0)
28    }
29    #[doc = "Bit 3 - The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access."]
30    #[inline(always)]
31    pub fn core1_dbus_acs_msk_dcache_st(&self) -> CORE1_DBUS_ACS_MSK_DCACHE_ST_R {
32        CORE1_DBUS_ACS_MSK_DCACHE_ST_R::new(((self.bits >> 3) & 1) != 0)
33    }
34    #[doc = "Bit 4 - The bit is used to indicate interrupt by authentication fail."]
35    #[inline(always)]
36    pub fn core1_dbus_reject_st(&self) -> CORE1_DBUS_REJECT_ST_R {
37        CORE1_DBUS_REJECT_ST_R::new(((self.bits >> 4) & 1) != 0)
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for R {
42    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
43        f.debug_struct("CORE1_ACS_CACHE_INT_ST")
44            .field(
45                "core1_ibus_acs_msk_icache_st",
46                &self.core1_ibus_acs_msk_icache_st(),
47            )
48            .field("core1_ibus_wr_icache_st", &self.core1_ibus_wr_icache_st())
49            .field("core1_ibus_reject_st", &self.core1_ibus_reject_st())
50            .field(
51                "core1_dbus_acs_msk_dcache_st",
52                &self.core1_dbus_acs_msk_dcache_st(),
53            )
54            .field("core1_dbus_reject_st", &self.core1_dbus_reject_st())
55            .finish()
56    }
57}
58#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core1_acs_cache_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
59pub struct CORE1_ACS_CACHE_INT_ST_SPEC;
60impl crate::RegisterSpec for CORE1_ACS_CACHE_INT_ST_SPEC {
61    type Ux = u32;
62}
63#[doc = "`read()` method returns [`core1_acs_cache_int_st::R`](R) reader structure"]
64impl crate::Readable for CORE1_ACS_CACHE_INT_ST_SPEC {}
65#[doc = "`reset()` method sets CORE1_ACS_CACHE_INT_ST to value 0"]
66impl crate::Resettable for CORE1_ACS_CACHE_INT_ST_SPEC {
67    const RESET_VALUE: u32 = 0;
68}
esp32s3/extmem/core1_acs_cache_int_st.rs

esp32s3/extmem/
core1_acs_cache_int_st.rs
