esp32s3/extmem/
cache_ilg_int_clr.rs

1#[doc = "Register `CACHE_ILG_INT_CLR` writer"]
2pub type W = crate::W<CACHE_ILG_INT_CLR_SPEC>;
3#[doc = "Field `ICACHE_SYNC_OP_FAULT` writer - The bit is used to clear interrupt by sync configurations fault."]
4pub type ICACHE_SYNC_OP_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` writer - The bit is used to clear interrupt by preload configurations fault."]
6pub type ICACHE_PRELOAD_OP_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `DCACHE_SYNC_OP_FAULT` writer - The bit is used to clear interrupt by sync configurations fault."]
8pub type DCACHE_SYNC_OP_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `DCACHE_PRELOAD_OP_FAULT` writer - The bit is used to clear interrupt by preload configurations fault."]
10pub type DCACHE_PRELOAD_OP_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `DCACHE_WRITE_FLASH` writer - The bit is used to clear interrupt by dcache trying to write flash."]
12pub type DCACHE_WRITE_FLASH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `MMU_ENTRY_FAULT` writer - The bit is used to clear interrupt by mmu entry fault."]
14pub type MMU_ENTRY_FAULT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `DCACHE_OCCUPY_EXC` writer - The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
16pub type DCACHE_OCCUPY_EXC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `IBUS_CNT_OVF` writer - The bit is used to clear interrupt by ibus counter overflow."]
18pub type IBUS_CNT_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `DBUS_CNT_OVF` writer - The bit is used to clear interrupt by dbus counter overflow."]
20pub type DBUS_CNT_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[cfg(feature = "impl-register-debug")]
22impl core::fmt::Debug for crate::generic::Reg<CACHE_ILG_INT_CLR_SPEC> {
23    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
24        write!(f, "(not readable)")
25    }
26}
27impl W {
28    #[doc = "Bit 0 - The bit is used to clear interrupt by sync configurations fault."]
29    #[inline(always)]
30    pub fn icache_sync_op_fault(&mut self) -> ICACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
31        ICACHE_SYNC_OP_FAULT_W::new(self, 0)
32    }
33    #[doc = "Bit 1 - The bit is used to clear interrupt by preload configurations fault."]
34    #[inline(always)]
35    pub fn icache_preload_op_fault(&mut self) -> ICACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
36        ICACHE_PRELOAD_OP_FAULT_W::new(self, 1)
37    }
38    #[doc = "Bit 2 - The bit is used to clear interrupt by sync configurations fault."]
39    #[inline(always)]
40    pub fn dcache_sync_op_fault(&mut self) -> DCACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
41        DCACHE_SYNC_OP_FAULT_W::new(self, 2)
42    }
43    #[doc = "Bit 3 - The bit is used to clear interrupt by preload configurations fault."]
44    #[inline(always)]
45    pub fn dcache_preload_op_fault(&mut self) -> DCACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
46        DCACHE_PRELOAD_OP_FAULT_W::new(self, 3)
47    }
48    #[doc = "Bit 4 - The bit is used to clear interrupt by dcache trying to write flash."]
49    #[inline(always)]
50    pub fn dcache_write_flash(&mut self) -> DCACHE_WRITE_FLASH_W<CACHE_ILG_INT_CLR_SPEC> {
51        DCACHE_WRITE_FLASH_W::new(self, 4)
52    }
53    #[doc = "Bit 5 - The bit is used to clear interrupt by mmu entry fault."]
54    #[inline(always)]
55    pub fn mmu_entry_fault(&mut self) -> MMU_ENTRY_FAULT_W<CACHE_ILG_INT_CLR_SPEC> {
56        MMU_ENTRY_FAULT_W::new(self, 5)
57    }
58    #[doc = "Bit 6 - The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
59    #[inline(always)]
60    pub fn dcache_occupy_exc(&mut self) -> DCACHE_OCCUPY_EXC_W<CACHE_ILG_INT_CLR_SPEC> {
61        DCACHE_OCCUPY_EXC_W::new(self, 6)
62    }
63    #[doc = "Bit 7 - The bit is used to clear interrupt by ibus counter overflow."]
64    #[inline(always)]
65    pub fn ibus_cnt_ovf(&mut self) -> IBUS_CNT_OVF_W<CACHE_ILG_INT_CLR_SPEC> {
66        IBUS_CNT_OVF_W::new(self, 7)
67    }
68    #[doc = "Bit 8 - The bit is used to clear interrupt by dbus counter overflow."]
69    #[inline(always)]
70    pub fn dbus_cnt_ovf(&mut self) -> DBUS_CNT_OVF_W<CACHE_ILG_INT_CLR_SPEC> {
71        DBUS_CNT_OVF_W::new(self, 8)
72    }
73}
74#[doc = "******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_ilg_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
75pub struct CACHE_ILG_INT_CLR_SPEC;
76impl crate::RegisterSpec for CACHE_ILG_INT_CLR_SPEC {
77    type Ux = u32;
78}
79#[doc = "`write(|w| ..)` method takes [`cache_ilg_int_clr::W`](W) writer structure"]
80impl crate::Writable for CACHE_ILG_INT_CLR_SPEC {
81    type Safety = crate::Unsafe;
82    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
83    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01ff;
84}
85#[doc = "`reset()` method sets CACHE_ILG_INT_CLR to value 0"]
86impl crate::Resettable for CACHE_ILG_INT_CLR_SPEC {
87    const RESET_VALUE: u32 = 0;
88}
esp32s3/extmem/cache_ilg_int_clr.rs

esp32s3/extmem/
cache_ilg_int_clr.rs
