1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 scl_low_period: SCL_LOW_PERIOD,
6 ctr: CTR,
7 sr: SR,
8 to: TO,
9 slave_addr: SLAVE_ADDR,
10 fifo_st: FIFO_ST,
11 fifo_conf: FIFO_CONF,
12 data: DATA,
13 int_raw: INT_RAW,
14 int_clr: INT_CLR,
15 int_ena: INT_ENA,
16 int_st: INT_ST,
17 sda_hold: SDA_HOLD,
18 sda_sample: SDA_SAMPLE,
19 scl_high_period: SCL_HIGH_PERIOD,
20 _reserved15: [u8; 0x04],
21 scl_start_hold: SCL_START_HOLD,
22 scl_rstart_setup: SCL_RSTART_SETUP,
23 scl_stop_hold: SCL_STOP_HOLD,
24 scl_stop_setup: SCL_STOP_SETUP,
25 filter_cfg: FILTER_CFG,
26 clk_conf: CLK_CONF,
27 comd: [COMD; 8],
28 scl_st_time_out: SCL_ST_TIME_OUT,
29 scl_main_st_time_out: SCL_MAIN_ST_TIME_OUT,
30 scl_sp_conf: SCL_SP_CONF,
31 scl_stretch_conf: SCL_STRETCH_CONF,
32 _reserved26: [u8; 0x70],
33 date: DATE,
34 _reserved27: [u8; 0x04],
35 txfifo_start_addr: TXFIFO_START_ADDR,
36 _reserved28: [u8; 0x7c],
37 rxfifo_start_addr: RXFIFO_START_ADDR,
38}
39impl RegisterBlock {
40 #[doc = "0x00 - Configures the low level width of the SCL Clock"]
41 #[inline(always)]
42 pub const fn scl_low_period(&self) -> &SCL_LOW_PERIOD {
43 &self.scl_low_period
44 }
45 #[doc = "0x04 - Transmission setting"]
46 #[inline(always)]
47 pub const fn ctr(&self) -> &CTR {
48 &self.ctr
49 }
50 #[doc = "0x08 - Describe I2C work status."]
51 #[inline(always)]
52 pub const fn sr(&self) -> &SR {
53 &self.sr
54 }
55 #[doc = "0x0c - Setting time out control for receiving data."]
56 #[inline(always)]
57 pub const fn to(&self) -> &TO {
58 &self.to
59 }
60 #[doc = "0x10 - Local slave address setting"]
61 #[inline(always)]
62 pub const fn slave_addr(&self) -> &SLAVE_ADDR {
63 &self.slave_addr
64 }
65 #[doc = "0x14 - FIFO status register."]
66 #[inline(always)]
67 pub const fn fifo_st(&self) -> &FIFO_ST {
68 &self.fifo_st
69 }
70 #[doc = "0x18 - FIFO configuration register."]
71 #[inline(always)]
72 pub const fn fifo_conf(&self) -> &FIFO_CONF {
73 &self.fifo_conf
74 }
75 #[doc = "0x1c - Rx FIFO read data."]
76 #[inline(always)]
77 pub const fn data(&self) -> &DATA {
78 &self.data
79 }
80 #[doc = "0x20 - Raw interrupt status"]
81 #[inline(always)]
82 pub const fn int_raw(&self) -> &INT_RAW {
83 &self.int_raw
84 }
85 #[doc = "0x24 - Interrupt clear bits"]
86 #[inline(always)]
87 pub const fn int_clr(&self) -> &INT_CLR {
88 &self.int_clr
89 }
90 #[doc = "0x28 - Interrupt enable bits"]
91 #[inline(always)]
92 pub const fn int_ena(&self) -> &INT_ENA {
93 &self.int_ena
94 }
95 #[doc = "0x2c - Status of captured I2C communication events"]
96 #[inline(always)]
97 pub const fn int_st(&self) -> &INT_ST {
98 &self.int_st
99 }
100 #[doc = "0x30 - Configures the hold time after a negative SCL edge."]
101 #[inline(always)]
102 pub const fn sda_hold(&self) -> &SDA_HOLD {
103 &self.sda_hold
104 }
105 #[doc = "0x34 - Configures the sample time after a positive SCL edge."]
106 #[inline(always)]
107 pub const fn sda_sample(&self) -> &SDA_SAMPLE {
108 &self.sda_sample
109 }
110 #[doc = "0x38 - Configures the high level width of SCL"]
111 #[inline(always)]
112 pub const fn scl_high_period(&self) -> &SCL_HIGH_PERIOD {
113 &self.scl_high_period
114 }
115 #[doc = "0x40 - Configures the delay between the SDA and SCL negative edge for a start condition"]
116 #[inline(always)]
117 pub const fn scl_start_hold(&self) -> &SCL_START_HOLD {
118 &self.scl_start_hold
119 }
120 #[doc = "0x44 - Configures the delay between the positive edge of SCL and the negative edge of SDA"]
121 #[inline(always)]
122 pub const fn scl_rstart_setup(&self) -> &SCL_RSTART_SETUP {
123 &self.scl_rstart_setup
124 }
125 #[doc = "0x48 - Configures the delay after the SCL clock edge for a stop condition"]
126 #[inline(always)]
127 pub const fn scl_stop_hold(&self) -> &SCL_STOP_HOLD {
128 &self.scl_stop_hold
129 }
130 #[doc = "0x4c - Configures the delay between the SDA and SCL positive edge for a stop condition"]
131 #[inline(always)]
132 pub const fn scl_stop_setup(&self) -> &SCL_STOP_SETUP {
133 &self.scl_stop_setup
134 }
135 #[doc = "0x50 - SCL and SDA filter configuration register"]
136 #[inline(always)]
137 pub const fn filter_cfg(&self) -> &FILTER_CFG {
138 &self.filter_cfg
139 }
140 #[doc = "0x54 - I2C CLK configuration register"]
141 #[inline(always)]
142 pub const fn clk_conf(&self) -> &CLK_CONF {
143 &self.clk_conf
144 }
145 #[doc = "0x58..0x78 - I2C command register %s"]
146 #[inline(always)]
147 pub const fn comd(&self, n: usize) -> &COMD {
148 &self.comd[n]
149 }
150 #[doc = "Iterator for array of:"]
151 #[doc = "0x58..0x78 - I2C command register %s"]
152 #[inline(always)]
153 pub fn comd_iter(&self) -> impl Iterator<Item = &COMD> {
154 self.comd.iter()
155 }
156 #[doc = "0x78 - SCL status time out register"]
157 #[inline(always)]
158 pub const fn scl_st_time_out(&self) -> &SCL_ST_TIME_OUT {
159 &self.scl_st_time_out
160 }
161 #[doc = "0x7c - SCL main status time out register"]
162 #[inline(always)]
163 pub const fn scl_main_st_time_out(&self) -> &SCL_MAIN_ST_TIME_OUT {
164 &self.scl_main_st_time_out
165 }
166 #[doc = "0x80 - Power configuration register"]
167 #[inline(always)]
168 pub const fn scl_sp_conf(&self) -> &SCL_SP_CONF {
169 &self.scl_sp_conf
170 }
171 #[doc = "0x84 - Set SCL stretch of I2C slave"]
172 #[inline(always)]
173 pub const fn scl_stretch_conf(&self) -> &SCL_STRETCH_CONF {
174 &self.scl_stretch_conf
175 }
176 #[doc = "0xf8 - Version register"]
177 #[inline(always)]
178 pub const fn date(&self) -> &DATE {
179 &self.date
180 }
181 #[doc = "0x100 - I2C TXFIFO base address register"]
182 #[inline(always)]
183 pub const fn txfifo_start_addr(&self) -> &TXFIFO_START_ADDR {
184 &self.txfifo_start_addr
185 }
186 #[doc = "0x180 - I2C RXFIFO base address register"]
187 #[inline(always)]
188 pub const fn rxfifo_start_addr(&self) -> &RXFIFO_START_ADDR {
189 &self.rxfifo_start_addr
190 }
191}
192#[doc = "SCL_LOW_PERIOD (rw) register accessor: Configures the low level width of the SCL Clock\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_low_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_low_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_low_period`] module"]
193pub type SCL_LOW_PERIOD = crate::Reg<scl_low_period::SCL_LOW_PERIOD_SPEC>;
194#[doc = "Configures the low level width of the SCL Clock"]
195pub mod scl_low_period;
196#[doc = "CTR (rw) register accessor: Transmission setting\n\nYou can [`read`](crate::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"]
197pub type CTR = crate::Reg<ctr::CTR_SPEC>;
198#[doc = "Transmission setting"]
199pub mod ctr;
200#[doc = "SR (r) register accessor: Describe I2C work status.\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"]
201pub type SR = crate::Reg<sr::SR_SPEC>;
202#[doc = "Describe I2C work status."]
203pub mod sr;
204#[doc = "TO (rw) register accessor: Setting time out control for receiving data.\n\nYou can [`read`](crate::Reg::read) this register and get [`to::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`to::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@to`] module"]
205pub type TO = crate::Reg<to::TO_SPEC>;
206#[doc = "Setting time out control for receiving data."]
207pub mod to;
208#[doc = "SLAVE_ADDR (rw) register accessor: Local slave address setting\n\nYou can [`read`](crate::Reg::read) this register and get [`slave_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slave_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slave_addr`] module"]
209pub type SLAVE_ADDR = crate::Reg<slave_addr::SLAVE_ADDR_SPEC>;
210#[doc = "Local slave address setting"]
211pub mod slave_addr;
212#[doc = "FIFO_ST (r) register accessor: FIFO status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_st`] module"]
213pub type FIFO_ST = crate::Reg<fifo_st::FIFO_ST_SPEC>;
214#[doc = "FIFO status register."]
215pub mod fifo_st;
216#[doc = "FIFO_CONF (rw) register accessor: FIFO configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_conf`] module"]
217pub type FIFO_CONF = crate::Reg<fifo_conf::FIFO_CONF_SPEC>;
218#[doc = "FIFO configuration register."]
219pub mod fifo_conf;
220#[doc = "DATA (rw) register accessor: Rx FIFO read data.\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
221pub type DATA = crate::Reg<data::DATA_SPEC>;
222#[doc = "Rx FIFO read data."]
223pub mod data;
224#[doc = "INT_RAW (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
225pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
226#[doc = "Raw interrupt status"]
227pub mod int_raw;
228#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
229pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
230#[doc = "Interrupt clear bits"]
231pub mod int_clr;
232#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
233pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
234#[doc = "Interrupt enable bits"]
235pub mod int_ena;
236#[doc = "INT_ST (r) register accessor: Status of captured I2C communication events\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
237pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
238#[doc = "Status of captured I2C communication events"]
239pub mod int_st;
240#[doc = "SDA_HOLD (rw) register accessor: Configures the hold time after a negative SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"]
241pub type SDA_HOLD = crate::Reg<sda_hold::SDA_HOLD_SPEC>;
242#[doc = "Configures the hold time after a negative SCL edge."]
243pub mod sda_hold;
244#[doc = "SDA_SAMPLE (rw) register accessor: Configures the sample time after a positive SCL edge.\n\nYou can [`read`](crate::Reg::read) this register and get [`sda_sample::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sda_sample::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_sample`] module"]
245pub type SDA_SAMPLE = crate::Reg<sda_sample::SDA_SAMPLE_SPEC>;
246#[doc = "Configures the sample time after a positive SCL edge."]
247pub mod sda_sample;
248#[doc = "SCL_HIGH_PERIOD (rw) register accessor: Configures the high level width of SCL\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_high_period::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_high_period::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_high_period`] module"]
249pub type SCL_HIGH_PERIOD = crate::Reg<scl_high_period::SCL_HIGH_PERIOD_SPEC>;
250#[doc = "Configures the high level width of SCL"]
251pub mod scl_high_period;
252#[doc = "SCL_START_HOLD (rw) register accessor: Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_start_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_start_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_start_hold`] module"]
253pub type SCL_START_HOLD = crate::Reg<scl_start_hold::SCL_START_HOLD_SPEC>;
254#[doc = "Configures the delay between the SDA and SCL negative edge for a start condition"]
255pub mod scl_start_hold;
256#[doc = "SCL_RSTART_SETUP (rw) register accessor: Configures the delay between the positive edge of SCL and the negative edge of SDA\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_rstart_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_rstart_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_rstart_setup`] module"]
257pub type SCL_RSTART_SETUP = crate::Reg<scl_rstart_setup::SCL_RSTART_SETUP_SPEC>;
258#[doc = "Configures the delay between the positive edge of SCL and the negative edge of SDA"]
259pub mod scl_rstart_setup;
260#[doc = "SCL_STOP_HOLD (rw) register accessor: Configures the delay after the SCL clock edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_stop_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_stop_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_hold`] module"]
261pub type SCL_STOP_HOLD = crate::Reg<scl_stop_hold::SCL_STOP_HOLD_SPEC>;
262#[doc = "Configures the delay after the SCL clock edge for a stop condition"]
263pub mod scl_stop_hold;
264#[doc = "SCL_STOP_SETUP (rw) register accessor: Configures the delay between the SDA and SCL positive edge for a stop condition\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_stop_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_stop_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_setup`] module"]
265pub type SCL_STOP_SETUP = crate::Reg<scl_stop_setup::SCL_STOP_SETUP_SPEC>;
266#[doc = "Configures the delay between the SDA and SCL positive edge for a stop condition"]
267pub mod scl_stop_setup;
268#[doc = "FILTER_CFG (rw) register accessor: SCL and SDA filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_cfg`] module"]
269pub type FILTER_CFG = crate::Reg<filter_cfg::FILTER_CFG_SPEC>;
270#[doc = "SCL and SDA filter configuration register"]
271pub mod filter_cfg;
272#[doc = "CLK_CONF (rw) register accessor: I2C CLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"]
273pub type CLK_CONF = crate::Reg<clk_conf::CLK_CONF_SPEC>;
274#[doc = "I2C CLK configuration register"]
275pub mod clk_conf;
276#[doc = "COMD (rw) register accessor: I2C command register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`comd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`comd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd`] module"]
277pub type COMD = crate::Reg<comd::COMD_SPEC>;
278#[doc = "I2C command register %s"]
279pub mod comd;
280#[doc = "SCL_ST_TIME_OUT (rw) register accessor: SCL status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_st_time_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_st_time_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_st_time_out`] module"]
281pub type SCL_ST_TIME_OUT = crate::Reg<scl_st_time_out::SCL_ST_TIME_OUT_SPEC>;
282#[doc = "SCL status time out register"]
283pub mod scl_st_time_out;
284#[doc = "SCL_MAIN_ST_TIME_OUT (rw) register accessor: SCL main status time out register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_main_st_time_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_main_st_time_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_main_st_time_out`] module"]
285pub type SCL_MAIN_ST_TIME_OUT = crate::Reg<scl_main_st_time_out::SCL_MAIN_ST_TIME_OUT_SPEC>;
286#[doc = "SCL main status time out register"]
287pub mod scl_main_st_time_out;
288#[doc = "SCL_SP_CONF (rw) register accessor: Power configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_sp_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_sp_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_sp_conf`] module"]
289pub type SCL_SP_CONF = crate::Reg<scl_sp_conf::SCL_SP_CONF_SPEC>;
290#[doc = "Power configuration register"]
291pub mod scl_sp_conf;
292#[doc = "SCL_STRETCH_CONF (rw) register accessor: Set SCL stretch of I2C slave\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_stretch_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_stretch_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stretch_conf`] module"]
293pub type SCL_STRETCH_CONF = crate::Reg<scl_stretch_conf::SCL_STRETCH_CONF_SPEC>;
294#[doc = "Set SCL stretch of I2C slave"]
295pub mod scl_stretch_conf;
296#[doc = "DATE (rw) register accessor: Version register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
297pub type DATE = crate::Reg<date::DATE_SPEC>;
298#[doc = "Version register"]
299pub mod date;
300#[doc = "TXFIFO_START_ADDR (r) register accessor: I2C TXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifo_start_addr`] module"]
301pub type TXFIFO_START_ADDR = crate::Reg<txfifo_start_addr::TXFIFO_START_ADDR_SPEC>;
302#[doc = "I2C TXFIFO base address register"]
303pub mod txfifo_start_addr;
304#[doc = "RXFIFO_START_ADDR (r) register accessor: I2C RXFIFO base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifo_start_addr`] module"]
305pub type RXFIFO_START_ADDR = crate::Reg<rxfifo_start_addr::RXFIFO_START_ADDR_SPEC>;
306#[doc = "I2C RXFIFO base address register"]
307pub mod rxfifo_start_addr;