esp32s3::spi0

Module ddr

Source
Expand description

SPI0 flash DDR mode control register

Structs§

  • DDR_SPEC
    SPI0 flash DDR mode control register

Type Aliases§

  • R
    Register DDR reader
  • SPI_FMEM_CLK_DIFF_EN_R
    Field SPI_FMEM_CLK_DIFF_EN reader - Set this bit to enable the differential SPI_CLK#.
  • SPI_FMEM_CLK_DIFF_EN_W
    Field SPI_FMEM_CLK_DIFF_EN writer - Set this bit to enable the differential SPI_CLK#.
  • SPI_FMEM_CLK_DIFF_INV_R
    Field SPI_FMEM_CLK_DIFF_INV reader - Set this bit to invert SPI_DIFF when accesses to flash. .
  • SPI_FMEM_CLK_DIFF_INV_W
    Field SPI_FMEM_CLK_DIFF_INV writer - Set this bit to invert SPI_DIFF when accesses to flash. .
  • SPI_FMEM_DDR_CMD_DIS_R
    Field SPI_FMEM_DDR_CMD_DIS reader - the bit is used to disable dual edge in CMD phase when ddr mode.
  • SPI_FMEM_DDR_CMD_DIS_W
    Field SPI_FMEM_DDR_CMD_DIS writer - the bit is used to disable dual edge in CMD phase when ddr mode.
  • SPI_FMEM_DDR_DQS_LOOP_MODE_R
    Field SPI_FMEM_DDR_DQS_LOOP_MODE reader - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.
  • SPI_FMEM_DDR_DQS_LOOP_MODE_W
    Field SPI_FMEM_DDR_DQS_LOOP_MODE writer - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.
  • SPI_FMEM_DDR_DQS_LOOP_R
    Field SPI_FMEM_DDR_DQS_LOOP reader - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module
  • SPI_FMEM_DDR_DQS_LOOP_W
    Field SPI_FMEM_DDR_DQS_LOOP writer - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module
  • SPI_FMEM_DDR_EN_R
    Field SPI_FMEM_DDR_EN reader - 1: in ddr mode, 0 in sdr mode
  • SPI_FMEM_DDR_EN_W
    Field SPI_FMEM_DDR_EN writer - 1: in ddr mode, 0 in sdr mode
  • SPI_FMEM_DDR_RDAT_SWP_R
    Field SPI_FMEM_DDR_RDAT_SWP reader - Set the bit to reorder RX data of the word in DDR mode.
  • SPI_FMEM_DDR_RDAT_SWP_W
    Field SPI_FMEM_DDR_RDAT_SWP writer - Set the bit to reorder RX data of the word in DDR mode.
  • SPI_FMEM_DDR_WDAT_SWP_R
    Field SPI_FMEM_DDR_WDAT_SWP reader - Set the bit to swap TX data of a word in DDR mode.
  • SPI_FMEM_DDR_WDAT_SWP_W
    Field SPI_FMEM_DDR_WDAT_SWP writer - Set the bit to swap TX data of a word in DDR mode.
  • SPI_FMEM_DQS_CA_IN_R
    Field SPI_FMEM_DQS_CA_IN reader - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  • SPI_FMEM_DQS_CA_IN_W
    Field SPI_FMEM_DQS_CA_IN writer - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
  • SPI_FMEM_HYPERBUS_CA_R
    Field SPI_FMEM_HYPERBUS_CA reader - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13’d0, spi_usr_addr_value[3:1]}.
  • SPI_FMEM_HYPERBUS_CA_W
    Field SPI_FMEM_HYPERBUS_CA writer - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13’d0, spi_usr_addr_value[3:1]}.
  • SPI_FMEM_HYPERBUS_DUMMY_2X_R
    Field SPI_FMEM_HYPERBUS_DUMMY_2X reader - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.
  • SPI_FMEM_HYPERBUS_DUMMY_2X_W
    Field SPI_FMEM_HYPERBUS_DUMMY_2X writer - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.
  • SPI_FMEM_HYPERBUS_MODE_R
    Field SPI_FMEM_HYPERBUS_MODE reader - Set this bit to enable the SPI HyperBus mode.
  • SPI_FMEM_HYPERBUS_MODE_W
    Field SPI_FMEM_HYPERBUS_MODE writer - Set this bit to enable the SPI HyperBus mode.
  • SPI_FMEM_OCTA_RAM_ADDR_R
    Field SPI_FMEM_OCTA_RAM_ADDR reader - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6’d0, spi_usr_addr_value[3:1], 1’b0}.
  • SPI_FMEM_OCTA_RAM_ADDR_W
    Field SPI_FMEM_OCTA_RAM_ADDR writer - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6’d0, spi_usr_addr_value[3:1], 1’b0}.
  • SPI_FMEM_OUTMINBYTELEN_R
    Field SPI_FMEM_OUTMINBYTELEN reader - It is the minimum output data length in the panda device.
  • SPI_FMEM_OUTMINBYTELEN_W
    Field SPI_FMEM_OUTMINBYTELEN writer - It is the minimum output data length in the panda device.
  • SPI_FMEM_RX_DDR_MSK_EN_R
    Field SPI_FMEM_RX_DDR_MSK_EN reader - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.
  • SPI_FMEM_RX_DDR_MSK_EN_W
    Field SPI_FMEM_RX_DDR_MSK_EN writer - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.
  • SPI_FMEM_TX_DDR_MSK_EN_R
    Field SPI_FMEM_TX_DDR_MSK_EN reader - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash.
  • SPI_FMEM_TX_DDR_MSK_EN_W
    Field SPI_FMEM_TX_DDR_MSK_EN writer - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash.
  • SPI_FMEM_USR_DDR_DQS_THD_R
    Field SPI_FMEM_USR_DDR_DQS_THD reader - The delay number of data strobe which from memory based on SPI_CLK.
  • SPI_FMEM_USR_DDR_DQS_THD_W
    Field SPI_FMEM_USR_DDR_DQS_THD writer - The delay number of data strobe which from memory based on SPI_CLK.
  • SPI_FMEM_VAR_DUMMY_R
    Field SPI_FMEM_VAR_DUMMY reader - Set the bit to enable variable dummy cycle in DDR mode.
  • SPI_FMEM_VAR_DUMMY_W
    Field SPI_FMEM_VAR_DUMMY writer - Set the bit to enable variable dummy cycle in DDR mode.
  • W
    Register DDR writer