Module esp32s3::dma

source ·
Expand description

DMA (Direct Memory Access) Controller

Re-exports§

  • pub use self::ch::CH;

Modules§

  • reserved
  • Cluster Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_WIGHT_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_WIGHT_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?
  • Version control register
  • Reject address accessing external RAM
  • Interrupt clear bits of external RAM permission
  • Interrupt enable bits of external RAM permission
  • Raw interrupt status of external RAM permission
  • Masked interrupt status of external RAM permission
  • Reject status accessing external RAM
  • Receive L2 FIFO depth of Rx channel 0
  • MISC register
  • Transmit L2 FIFO depth of Tx channel 0
  • reserved

Structs§

Type Aliases§

  • AHB_TEST (rw) register accessor: reserved
  • DATE (rw) register accessor: Version control register
  • EXTMEM_REJECT_ADDR (r) register accessor: Reject address accessing external RAM
  • EXTMEM_REJECT_INT_CLR (w) register accessor: Interrupt clear bits of external RAM permission
  • EXTMEM_REJECT_INT_ENA (rw) register accessor: Interrupt enable bits of external RAM permission
  • EXTMEM_REJECT_INT_RAW (rw) register accessor: Raw interrupt status of external RAM permission
  • EXTMEM_REJECT_INT_ST (r) register accessor: Masked interrupt status of external RAM permission
  • EXTMEM_REJECT_ST (r) register accessor: Reject status accessing external RAM
  • IN_SRAM_SIZE_CH (rw) register accessor: Receive L2 FIFO depth of Rx channel 0
  • MISC_CONF (rw) register accessor: MISC register
  • OUT_SRAM_SIZE_CH (rw) register accessor: Transmit L2 FIFO depth of Tx channel 0
  • PD_CONF (rw) register accessor: reserved