Module esp32s3::usb_device 
source · Expand description
Full-speed USB Serial/JTAG Controller
Modules§
- Configure 0 register
 - Version control register
 - Endpoint 1 FIFO register
 - Endpoint 1 configure and status register
 - SOF frame number
 - IN Endpoint 0 status
 - IN Endpoint 1 status
 - IN Endpoint 2 status
 - IN Endpoint 3 status
 - Interrupt clear bits
 - Interrupt enable bits
 - Raw status interrupt
 - Masked interrupt
 - USB-JTAG FIFO status
 - Power control
 - MISC register
 - OUT Endpoint 0 status
 - OUT Endpoint 1 status
 - OUT Endpoint 2 status
 - USB Internal PHY test register
 
Structs§
- Register block
 
Type Aliases§
- CONF0 (rw) register accessor: Configure 0 register
 - DATE (rw) register accessor: Version control register
 - EP1 (rw) register accessor: Endpoint 1 FIFO register
 - EP1_CONF (rw) register accessor: Endpoint 1 configure and status register
 - FRAM_NUM (r) register accessor: SOF frame number
 - INT_CLR (w) register accessor: Interrupt clear bits
 - INT_ENA (rw) register accessor: Interrupt enable bits
 - INT_RAW (rw) register accessor: Raw status interrupt
 - INT_ST (r) register accessor: Masked interrupt
 - IN_EP0_ST (r) register accessor: IN Endpoint 0 status
 - IN_EP1_ST (r) register accessor: IN Endpoint 1 status
 - IN_EP2_ST (r) register accessor: IN Endpoint 2 status
 - IN_EP3_ST (r) register accessor: IN Endpoint 3 status
 - JFIFO_ST (rw) register accessor: USB-JTAG FIFO status
 - MEM_CONF (rw) register accessor: Power control
 - MISC_CONF (rw) register accessor: MISC register
 - OUT_EP0_ST (r) register accessor: OUT Endpoint 0 status
 - OUT_EP1_ST (r) register accessor: OUT Endpoint 1 status
 - OUT_EP2_ST (r) register accessor: OUT Endpoint 2 status
 - TEST (rw) register accessor: USB Internal PHY test register