Module esp32s3::lcd_cam::cam_ctrl

Camera clock configuration register

Structs

• CAM_CTRL_SPEC
  Camera clock configuration register

Type Aliases

• CAM_BIT_ORDER_R
  Field CAM_BIT_ORDER reader - 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in 8-bit mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change.
• CAM_BIT_ORDER_W
  Field CAM_BIT_ORDER writer - 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in 8-bit mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change.
• CAM_BYTE_ORDER_R
  Field CAM_BYTE_ORDER reader - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change.
• CAM_BYTE_ORDER_W
  Field CAM_BYTE_ORDER writer - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change.
• CAM_CLKM_DIV_A_R
  Field CAM_CLKM_DIV_A reader - Fractional clock divider denominator value.
• CAM_CLKM_DIV_A_W
  Field CAM_CLKM_DIV_A writer - Fractional clock divider denominator value.
• CAM_CLKM_DIV_B_R
  Field CAM_CLKM_DIV_B reader - Fractional clock divider numerator value.
• CAM_CLKM_DIV_B_W
  Field CAM_CLKM_DIV_B writer - Fractional clock divider numerator value.
• CAM_CLKM_DIV_NUM_R
  Field CAM_CLKM_DIV_NUM reader - Integral camera clock divider value.
• CAM_CLKM_DIV_NUM_W
  Field CAM_CLKM_DIV_NUM writer - Integral camera clock divider value.
• CAM_CLK_SEL_R
  Field CAM_CLK_SEL reader - Select camera module source clock. 0: Clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK.
• CAM_CLK_SEL_W
  Field CAM_CLK_SEL writer - Select camera module source clock. 0: Clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK.
• CAM_LINE_INT_EN_R
  Field CAM_LINE_INT_EN reader - 1: Enable to generate LCD_CAM_CAM_HS_INT. 0: Disable.
• CAM_LINE_INT_EN_W
  Field CAM_LINE_INT_EN writer - 1: Enable to generate LCD_CAM_CAM_HS_INT. 0: Disable.
• CAM_STOP_EN_R
  Field CAM_STOP_EN reader - Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not stop.
• CAM_STOP_EN_W
  Field CAM_STOP_EN writer - Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not stop.
• CAM_UPDATE_R
  Field CAM_UPDATE reader - 1: Update camera registers. This bit is cleared by hardware. 0: Do not care.
• CAM_UPDATE_W
  Field CAM_UPDATE writer - 1: Update camera registers. This bit is cleared by hardware. 0: Do not care.
• CAM_VSYNC_FILTER_THRES_R
  Field CAM_VSYNC_FILTER_THRES reader - Filter threshold value for CAM_VSYNC signal.
• CAM_VSYNC_FILTER_THRES_W
  Field CAM_VSYNC_FILTER_THRES writer - Filter threshold value for CAM_VSYNC signal.
• CAM_VS_EOF_EN_R
  Field CAM_VS_EOF_EN reader - 1: Enable CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by LCD_CAM_CAM_REC_DATA_BYTELEN.
• CAM_VS_EOF_EN_W
  Field CAM_VS_EOF_EN writer - 1: Enable CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by LCD_CAM_CAM_REC_DATA_BYTELEN.
• R
  Register CAM_CTRL reader
• W
  Register CAM_CTRL writer