Module esp32s3::spi0::cache_sctrl

source ·
Expand description

SPI0 external RAM control register

Structs

Type Aliases

  • CACHE_SRAM_USR_RCMD_R
    Field CACHE_SRAM_USR_RCMD reader - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.
  • CACHE_SRAM_USR_RCMD_W
    Field CACHE_SRAM_USR_RCMD writer - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.
  • CACHE_SRAM_USR_WCMD_R
    Field CACHE_SRAM_USR_WCMD reader - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.
  • CACHE_SRAM_USR_WCMD_W
    Field CACHE_SRAM_USR_WCMD writer - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.
  • CACHE_USR_SCMD_4BYTE_R
    Field CACHE_USR_SCMD_4BYTE reader - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.
  • CACHE_USR_SCMD_4BYTE_W
    Field CACHE_USR_SCMD_4BYTE writer - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.
  • R
    Register CACHE_SCTRL reader
  • SRAM_ADDR_BITLEN_R
    Field SRAM_ADDR_BITLEN reader - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).
  • SRAM_ADDR_BITLEN_W
    Field SRAM_ADDR_BITLEN writer - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).
  • SRAM_OCT_R
    Field SRAM_OCT reader - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.
  • SRAM_OCT_W
    Field SRAM_OCT writer - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.
  • SRAM_RDUMMY_CYCLELEN_R
    Field SRAM_RDUMMY_CYCLELEN reader - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.
  • SRAM_RDUMMY_CYCLELEN_W
    Field SRAM_RDUMMY_CYCLELEN writer - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.
  • SRAM_WDUMMY_CYCLELEN_R
    Field SRAM_WDUMMY_CYCLELEN reader - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.
  • SRAM_WDUMMY_CYCLELEN_W
    Field SRAM_WDUMMY_CYCLELEN writer - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.
  • USR_RD_SRAM_DUMMY_R
    Field USR_RD_SRAM_DUMMY reader - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.
  • USR_RD_SRAM_DUMMY_W
    Field USR_RD_SRAM_DUMMY writer - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.
  • USR_SRAM_DIO_R
    Field USR_SRAM_DIO reader - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.
  • USR_SRAM_DIO_W
    Field USR_SRAM_DIO writer - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.
  • USR_SRAM_QIO_R
    Field USR_SRAM_QIO reader - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.
  • USR_SRAM_QIO_W
    Field USR_SRAM_QIO writer - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.
  • USR_WR_SRAM_DUMMY_R
    Field USR_WR_SRAM_DUMMY reader - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.
  • USR_WR_SRAM_DUMMY_W
    Field USR_WR_SRAM_DUMMY writer - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.
  • W
    Register CACHE_SCTRL writer