Expand description
DMA (Direct Memory Access) Controller
Modules
- reserved
- Version control register
- Reject address accessing external RAM
- Interrupt clear bits of external RAM permission
- Interrupt enable bits of external RAM permission
- Raw interrupt status of external RAM permission
- Masked interrupt status of external RAM permission
- Reject status accessing external RAM
- Configure 0 register of Rx channel 0
- Configure 1 register of Rx channel 0
- The last inlink descriptor address of Rx channel 0
- The second-to-last inlink descriptor address of Rx channel 0
- Current inlink descriptor address of Rx channel 0
- Inlink descriptor address when errors occur of Rx channel 0
- Interrupt clear bits of Rx channel 0
- Interrupt enable bits of Rx channel 0
- Raw status interrupt of Rx channel 0
- Masked interrupt of Rx channel 0
- Link descriptor configure and control register of Rx channel 0
- Peripheral selection of Rx channel 0
- Pop control register of Rx channel 0
- Priority register of Rx channel 0
- Receive L2 FIFO depth of Rx channel 0
- Receive status of Rx channel 0
- Inlink descriptor address when EOF occurs of Rx channel 0
- Weight register of Rx channel 0
- Receive FIFO status of Rx channel 0
- MISC register
- Configure 0 register of Tx channel 0
- Configure 1 register of Tx channel 0
- The last inlink descriptor address of Tx channel 0
- The second-to-last inlink descriptor address of Tx channel 0
- Current inlink descriptor address of Tx channel 0
- The last outlink descriptor address when EOF occurs of Tx channel 0
- Outlink descriptor address when EOF occurs of Tx channel 0
- Interrupt clear bits of Tx channel 0
- Interrupt enable bits of Tx channel 0
- Raw status interrupt of Tx channel 0
- Masked interrupt of Tx channel 0
- Link descriptor configure and control register of Tx channel 0
- Peripheral selection of Tx channel 0
- Priority register of Tx channel 0.
- Push control register of Rx channel 0
- Transmit L2 FIFO depth of Tx channel 0
- Transmit status of Tx channel 0
- Weight register of Rx channel 0
- Transmit FIFO status of Tx channel 0
- reserved
Structs
- Register block
Type Aliases
- AHB_TEST (rw) register accessor: reserved
- DATE (rw) register accessor: Version control register
- EXTMEM_REJECT_ADDR (r) register accessor: Reject address accessing external RAM
- EXTMEM_REJECT_INT_CLR (w) register accessor: Interrupt clear bits of external RAM permission
- EXTMEM_REJECT_INT_ENA (rw) register accessor: Interrupt enable bits of external RAM permission
- EXTMEM_REJECT_INT_RAW (rw) register accessor: Raw interrupt status of external RAM permission
- EXTMEM_REJECT_INT_ST (r) register accessor: Masked interrupt status of external RAM permission
- EXTMEM_REJECT_ST (r) register accessor: Reject status accessing external RAM
- INFIFO_STATUS_CH (r) register accessor: Receive FIFO status of Rx channel 0
- IN_CONF0_CH (rw) register accessor: Configure 0 register of Rx channel 0
- IN_CONF1_CH (rw) register accessor: Configure 1 register of Rx channel 0
- IN_DSCR_BF0_CH (r) register accessor: The last inlink descriptor address of Rx channel 0
- IN_DSCR_BF1_CH (r) register accessor: The second-to-last inlink descriptor address of Rx channel 0
- IN_DSCR_CH (r) register accessor: Current inlink descriptor address of Rx channel 0
- IN_ERR_EOF_DES_ADDR_CH (r) register accessor: Inlink descriptor address when errors occur of Rx channel 0
- IN_INT_CLR_CH (w) register accessor: Interrupt clear bits of Rx channel 0
- IN_INT_ENA_CH (rw) register accessor: Interrupt enable bits of Rx channel 0
- IN_INT_RAW_CH (rw) register accessor: Raw status interrupt of Rx channel 0
- IN_INT_ST_CH (r) register accessor: Masked interrupt of Rx channel 0
- IN_LINK_CH (rw) register accessor: Link descriptor configure and control register of Rx channel 0
- IN_PERI_SEL_CH (rw) register accessor: Peripheral selection of Rx channel 0
- IN_POP_CH (rw) register accessor: Pop control register of Rx channel 0
- IN_PRI_CH (rw) register accessor: Priority register of Rx channel 0
- IN_SRAM_SIZE_CH (rw) register accessor: Receive L2 FIFO depth of Rx channel 0
- IN_STATE_CH (r) register accessor: Receive status of Rx channel 0
- IN_SUC_EOF_DES_ADDR_CH (r) register accessor: Inlink descriptor address when EOF occurs of Rx channel 0
- IN_WIGHT_CH (rw) register accessor: Weight register of Rx channel 0
- MISC_CONF (rw) register accessor: MISC register
- OUTFIFO_STATUS_CH (r) register accessor: Transmit FIFO status of Tx channel 0
- OUT_CONF0_CH (rw) register accessor: Configure 0 register of Tx channel 0
- OUT_CONF1_CH (rw) register accessor: Configure 1 register of Tx channel 0
- OUT_DSCR_BF0_CH (r) register accessor: The last inlink descriptor address of Tx channel 0
- OUT_DSCR_BF1_CH (r) register accessor: The second-to-last inlink descriptor address of Tx channel 0
- OUT_DSCR_CH (r) register accessor: Current inlink descriptor address of Tx channel 0
- OUT_EOF_BFR_DES_ADDR_CH (r) register accessor: The last outlink descriptor address when EOF occurs of Tx channel 0
- OUT_EOF_DES_ADDR_CH (r) register accessor: Outlink descriptor address when EOF occurs of Tx channel 0
- OUT_INT_CLR_CH (w) register accessor: Interrupt clear bits of Tx channel 0
- OUT_INT_ENA_CH (rw) register accessor: Interrupt enable bits of Tx channel 0
- OUT_INT_RAW_CH (rw) register accessor: Raw status interrupt of Tx channel 0
- OUT_INT_ST_CH (r) register accessor: Masked interrupt of Tx channel 0
- OUT_LINK_CH (rw) register accessor: Link descriptor configure and control register of Tx channel 0
- OUT_PERI_SEL_CH (rw) register accessor: Peripheral selection of Tx channel 0
- OUT_PRI_CH (rw) register accessor: Priority register of Tx channel 0.
- OUT_PUSH_CH (rw) register accessor: Push control register of Rx channel 0
- OUT_SRAM_SIZE_CH (rw) register accessor: Transmit L2 FIFO depth of Tx channel 0
- OUT_STATE_CH (r) register accessor: Transmit status of Tx channel 0
- OUT_WIGHT_CH (rw) register accessor: Weight register of Rx channel 0
- PD_CONF (rw) register accessor: reserved