Module esp32s3::spi2::ctrl

Expand description

SPI control register

Structs

SPI control register

Field DUMMY_OUT reader - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.

DUMMY_OUT_W

Field DUMMY_OUT writer - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.

D_POL_R

Field D_POL reader - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.

D_POL_W

Field D_POL writer - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.

FADDR_DUAL_R

Field FADDR_DUAL reader - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

FADDR_DUAL_W

Field FADDR_DUAL writer - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

FADDR_OCT_R

Field FADDR_OCT reader - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

FADDR_OCT_W

Field FADDR_OCT writer - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

FADDR_QUAD_R

Field FADDR_QUAD reader - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

FADDR_QUAD_W

Field FADDR_QUAD writer - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

FCMD_DUAL_R

Field FCMD_DUAL reader - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

FCMD_DUAL_W

Field FCMD_DUAL writer - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

FCMD_OCT_R

Field FCMD_OCT reader - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

FCMD_OCT_W

Field FCMD_OCT writer - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

FCMD_QUAD_R

Field FCMD_QUAD reader - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

FCMD_QUAD_W

Field FCMD_QUAD writer - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

FREAD_DUAL_R

Field FREAD_DUAL reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.

FREAD_DUAL_W

Field FREAD_DUAL writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.

FREAD_OCT_R

Field FREAD_OCT reader - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.

FREAD_OCT_W

Field FREAD_OCT writer - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.

FREAD_QUAD_R

Field FREAD_QUAD reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.

FREAD_QUAD_W

Field FREAD_QUAD writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.

HOLD_POL_R

Field HOLD_POL reader - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.

HOLD_POL_W

Field HOLD_POL writer - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.

Q_POL_R

Field Q_POL reader - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.

Q_POL_W

Field Q_POL writer - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.

R

Register CTRL reader

RD_BIT_ORDER_R

Field RD_BIT_ORDER reader - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.

RD_BIT_ORDER_W

Field RD_BIT_ORDER writer - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.

W

Register CTRL writer

WP_POL_R

Field WP_POL reader - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.

WP_POL_W

Field WP_POL writer - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.

WR_BIT_ORDER_R

Field WR_BIT_ORDER reader - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.

WR_BIT_ORDER_W

Field WR_BIT_ORDER writer - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.