Module esp32s3::extmem::core0_acs_cache_int_st

******* Description ***********

Structs

• CORE0_ACS_CACHE_INT_ST_SPEC
  ******* Description ***********
• R
  Register CORE0_ACS_CACHE_INT_ST reader

Type Definitions

• CORE0_DBUS_ACS_MSK_DCACHE_ST_R
  Field CORE0_DBUS_ACS_MSK_DCACHE_ST reader - The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.
• CORE0_DBUS_REJECT_ST_R
  Field CORE0_DBUS_REJECT_ST reader - The bit is used to indicate interrupt by authentication fail.
• CORE0_IBUS_ACS_MSK_ICACHE_ST_R
  Field CORE0_IBUS_ACS_MSK_ICACHE_ST reader - The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.
• CORE0_IBUS_REJECT_ST_R
  Field CORE0_IBUS_REJECT_ST reader - The bit is used to indicate interrupt by authentication fail.
• CORE0_IBUS_WR_ICACHE_ST_R
  Field CORE0_IBUS_WR_ICACHE_ST reader - The bit is used to indicate interrupt by ibus trying to write icache