esp32s3_ulp/sens/
sar_i2c_ctrl.rs

1#[doc = "Register `SAR_I2C_CTRL` reader"]
2pub type R = crate::R<SAR_I2C_CTRL_SPEC>;
3#[doc = "Register `SAR_I2C_CTRL` writer"]
4pub type W = crate::W<SAR_I2C_CTRL_SPEC>;
5#[doc = "Field `SAR_I2C_CTRL` reader - I2C control data only active when reg_sar_i2c_start_force = 1"]
6pub type SAR_I2C_CTRL_R = crate::FieldReader<u32>;
7#[doc = "Field `SAR_I2C_CTRL` writer - I2C control data only active when reg_sar_i2c_start_force = 1"]
8pub type SAR_I2C_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
9#[doc = "Field `SAR_I2C_START` reader - start I2C only active when reg_sar_i2c_start_force = 1"]
10pub type SAR_I2C_START_R = crate::BitReader;
11#[doc = "Field `SAR_I2C_START` writer - start I2C only active when reg_sar_i2c_start_force = 1"]
12pub type SAR_I2C_START_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SAR_I2C_START_FORCE` reader - 1: I2C started by SW 0: I2C started by FSM"]
14pub type SAR_I2C_START_FORCE_R = crate::BitReader;
15#[doc = "Field `SAR_I2C_START_FORCE` writer - 1: I2C started by SW 0: I2C started by FSM"]
16pub type SAR_I2C_START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 0:27 - I2C control data only active when reg_sar_i2c_start_force = 1"]
19    #[inline(always)]
20    pub fn sar_i2c_ctrl(&self) -> SAR_I2C_CTRL_R {
21        SAR_I2C_CTRL_R::new(self.bits & 0x0fff_ffff)
22    }
23    #[doc = "Bit 28 - start I2C only active when reg_sar_i2c_start_force = 1"]
24    #[inline(always)]
25    pub fn sar_i2c_start(&self) -> SAR_I2C_START_R {
26        SAR_I2C_START_R::new(((self.bits >> 28) & 1) != 0)
27    }
28    #[doc = "Bit 29 - 1: I2C started by SW 0: I2C started by FSM"]
29    #[inline(always)]
30    pub fn sar_i2c_start_force(&self) -> SAR_I2C_START_FORCE_R {
31        SAR_I2C_START_FORCE_R::new(((self.bits >> 29) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("SAR_I2C_CTRL")
38            .field("sar_i2c_ctrl", &self.sar_i2c_ctrl())
39            .field("sar_i2c_start", &self.sar_i2c_start())
40            .field("sar_i2c_start_force", &self.sar_i2c_start_force())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:27 - I2C control data only active when reg_sar_i2c_start_force = 1"]
46    #[inline(always)]
47    #[must_use]
48    pub fn sar_i2c_ctrl(&mut self) -> SAR_I2C_CTRL_W<SAR_I2C_CTRL_SPEC> {
49        SAR_I2C_CTRL_W::new(self, 0)
50    }
51    #[doc = "Bit 28 - start I2C only active when reg_sar_i2c_start_force = 1"]
52    #[inline(always)]
53    #[must_use]
54    pub fn sar_i2c_start(&mut self) -> SAR_I2C_START_W<SAR_I2C_CTRL_SPEC> {
55        SAR_I2C_START_W::new(self, 28)
56    }
57    #[doc = "Bit 29 - 1: I2C started by SW 0: I2C started by FSM"]
58    #[inline(always)]
59    #[must_use]
60    pub fn sar_i2c_start_force(&mut self) -> SAR_I2C_START_FORCE_W<SAR_I2C_CTRL_SPEC> {
61        SAR_I2C_START_FORCE_W::new(self, 29)
62    }
63}
64#[doc = "configure rtc i2c controller by sw\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_i2c_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_i2c_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct SAR_I2C_CTRL_SPEC;
66impl crate::RegisterSpec for SAR_I2C_CTRL_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`sar_i2c_ctrl::R`](R) reader structure"]
70impl crate::Readable for SAR_I2C_CTRL_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`sar_i2c_ctrl::W`](W) writer structure"]
72impl crate::Writable for SAR_I2C_CTRL_SPEC {
73    type Safety = crate::Unsafe;
74    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
76}
77#[doc = "`reset()` method sets SAR_I2C_CTRL to value 0"]
78impl crate::Resettable for SAR_I2C_CTRL_SPEC {
79    const RESET_VALUE: u32 = 0;
80}
esp32s3_ulp/sens/sar_i2c_ctrl.rs

esp32s3_ulp/sens/
sar_i2c_ctrl.rs
