esp32s3_ulp/rtc_io/
sar_i2c_io.rs

1#[doc = "Register `SAR_I2C_IO` reader"]
2pub type R = crate::R<SAR_I2C_IO_SPEC>;
3#[doc = "Register `SAR_I2C_IO` writer"]
4pub type W = crate::W<SAR_I2C_IO_SPEC>;
5#[doc = "Field `SAR_DEBUG_BIT_SEL` reader - ******* Description configure***"]
6pub type SAR_DEBUG_BIT_SEL_R = crate::FieldReader;
7#[doc = "Field `SAR_DEBUG_BIT_SEL` writer - ******* Description configure***"]
8pub type SAR_DEBUG_BIT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `SAR_I2C_SCL_SEL` reader - ******* Description configure***"]
10pub type SAR_I2C_SCL_SEL_R = crate::FieldReader;
11#[doc = "Field `SAR_I2C_SCL_SEL` writer - ******* Description configure***"]
12pub type SAR_I2C_SCL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `SAR_I2C_SDA_SEL` reader - ******* Description configure***"]
14pub type SAR_I2C_SDA_SEL_R = crate::FieldReader;
15#[doc = "Field `SAR_I2C_SDA_SEL` writer - ******* Description configure***"]
16pub type SAR_I2C_SDA_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17impl R {
18    #[doc = "Bits 23:27 - ******* Description configure***"]
19    #[inline(always)]
20    pub fn sar_debug_bit_sel(&self) -> SAR_DEBUG_BIT_SEL_R {
21        SAR_DEBUG_BIT_SEL_R::new(((self.bits >> 23) & 0x1f) as u8)
22    }
23    #[doc = "Bits 28:29 - ******* Description configure***"]
24    #[inline(always)]
25    pub fn sar_i2c_scl_sel(&self) -> SAR_I2C_SCL_SEL_R {
26        SAR_I2C_SCL_SEL_R::new(((self.bits >> 28) & 3) as u8)
27    }
28    #[doc = "Bits 30:31 - ******* Description configure***"]
29    #[inline(always)]
30    pub fn sar_i2c_sda_sel(&self) -> SAR_I2C_SDA_SEL_R {
31        SAR_I2C_SDA_SEL_R::new(((self.bits >> 30) & 3) as u8)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("SAR_I2C_IO")
38            .field("sar_debug_bit_sel", &self.sar_debug_bit_sel())
39            .field("sar_i2c_scl_sel", &self.sar_i2c_scl_sel())
40            .field("sar_i2c_sda_sel", &self.sar_i2c_sda_sel())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 23:27 - ******* Description configure***"]
46    #[inline(always)]
47    #[must_use]
48    pub fn sar_debug_bit_sel(&mut self) -> SAR_DEBUG_BIT_SEL_W<SAR_I2C_IO_SPEC> {
49        SAR_DEBUG_BIT_SEL_W::new(self, 23)
50    }
51    #[doc = "Bits 28:29 - ******* Description configure***"]
52    #[inline(always)]
53    #[must_use]
54    pub fn sar_i2c_scl_sel(&mut self) -> SAR_I2C_SCL_SEL_W<SAR_I2C_IO_SPEC> {
55        SAR_I2C_SCL_SEL_W::new(self, 28)
56    }
57    #[doc = "Bits 30:31 - ******* Description configure***"]
58    #[inline(always)]
59    #[must_use]
60    pub fn sar_i2c_sda_sel(&mut self) -> SAR_I2C_SDA_SEL_W<SAR_I2C_IO_SPEC> {
61        SAR_I2C_SDA_SEL_W::new(self, 30)
62    }
63}
64#[doc = "configure rtc i2c mux\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_i2c_io::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_i2c_io::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct SAR_I2C_IO_SPEC;
66impl crate::RegisterSpec for SAR_I2C_IO_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`sar_i2c_io::R`](R) reader structure"]
70impl crate::Readable for SAR_I2C_IO_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`sar_i2c_io::W`](W) writer structure"]
72impl crate::Writable for SAR_I2C_IO_SPEC {
73    type Safety = crate::Unsafe;
74    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
76}
77#[doc = "`reset()` method sets SAR_I2C_IO to value 0"]
78impl crate::Resettable for SAR_I2C_IO_SPEC {
79    const RESET_VALUE: u32 = 0;
80}
esp32s3_ulp/rtc_io/sar_i2c_io.rs

esp32s3_ulp/rtc_io/
sar_i2c_io.rs
