esp32s3_ulp/rtc_i2c/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `SLAVE_TRAN_COMP` writer - clear slave transit complete interrupt"]
4pub type SLAVE_TRAN_COMP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `ARBITRATION_LOST` writer - clear arbitration lost interrupt"]
6pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `MASTER_TRAN_COMP` writer - clear master transit complete interrupt"]
8pub type MASTER_TRAN_COMP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `TRANS_COMPLETE` writer - clear transit complete interrupt"]
10pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `TIME_OUT` writer - clear time out interrupt"]
12pub type TIME_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ACK_ERR` writer - clear ack error interrupt"]
14pub type ACK_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `RX_DATA` writer - clear receive data interrupt"]
16pub type RX_DATA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TX_DATA` writer - clear transit load data complete interrupt"]
18pub type TX_DATA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `DETECT_START` writer - clear detect start interrupt"]
20pub type DETECT_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[cfg(feature = "impl-register-debug")]
22impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
23    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
24        write!(f, "(not readable)")
25    }
26}
27impl W {
28    #[doc = "Bit 0 - clear slave transit complete interrupt"]
29    #[inline(always)]
30    #[must_use]
31    pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_CLR_SPEC> {
32        SLAVE_TRAN_COMP_W::new(self, 0)
33    }
34    #[doc = "Bit 1 - clear arbitration lost interrupt"]
35    #[inline(always)]
36    #[must_use]
37    pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
38        ARBITRATION_LOST_W::new(self, 1)
39    }
40    #[doc = "Bit 2 - clear master transit complete interrupt"]
41    #[inline(always)]
42    #[must_use]
43    pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_CLR_SPEC> {
44        MASTER_TRAN_COMP_W::new(self, 2)
45    }
46    #[doc = "Bit 3 - clear transit complete interrupt"]
47    #[inline(always)]
48    #[must_use]
49    pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
50        TRANS_COMPLETE_W::new(self, 3)
51    }
52    #[doc = "Bit 4 - clear time out interrupt"]
53    #[inline(always)]
54    #[must_use]
55    pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
56        TIME_OUT_W::new(self, 4)
57    }
58    #[doc = "Bit 5 - clear ack error interrupt"]
59    #[inline(always)]
60    #[must_use]
61    pub fn ack_err(&mut self) -> ACK_ERR_W<INT_CLR_SPEC> {
62        ACK_ERR_W::new(self, 5)
63    }
64    #[doc = "Bit 6 - clear receive data interrupt"]
65    #[inline(always)]
66    #[must_use]
67    pub fn rx_data(&mut self) -> RX_DATA_W<INT_CLR_SPEC> {
68        RX_DATA_W::new(self, 6)
69    }
70    #[doc = "Bit 7 - clear transit load data complete interrupt"]
71    #[inline(always)]
72    #[must_use]
73    pub fn tx_data(&mut self) -> TX_DATA_W<INT_CLR_SPEC> {
74        TX_DATA_W::new(self, 7)
75    }
76    #[doc = "Bit 8 - clear detect start interrupt"]
77    #[inline(always)]
78    #[must_use]
79    pub fn detect_start(&mut self) -> DETECT_START_W<INT_CLR_SPEC> {
80        DETECT_START_W::new(self, 8)
81    }
82}
83#[doc = "interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
84pub struct INT_CLR_SPEC;
85impl crate::RegisterSpec for INT_CLR_SPEC {
86    type Ux = u32;
87}
88#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
89impl crate::Writable for INT_CLR_SPEC {
90    type Safety = crate::Unsafe;
91    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
92    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01ff;
93}
94#[doc = "`reset()` method sets INT_CLR to value 0"]
95impl crate::Resettable for INT_CLR_SPEC {
96    const RESET_VALUE: u32 = 0;
97}
esp32s3_ulp/rtc_i2c/int_clr.rs

esp32s3_ulp/rtc_i2c/
int_clr.rs
