esp32s3_ulp/rtc_cntl/
rtc_ulp_cp_timer_1.rs

1#[doc = "Register `RTC_ULP_CP_TIMER_1` reader"]
2pub type R = crate::R<RTC_ULP_CP_TIMER_1_SPEC>;
3#[doc = "Register `RTC_ULP_CP_TIMER_1` writer"]
4pub type W = crate::W<RTC_ULP_CP_TIMER_1_SPEC>;
5#[doc = "Field `ULP_CP_TIMER_SLP_CYCLE` reader - sleep cycles for ULP-coprocessor timer"]
6pub type ULP_CP_TIMER_SLP_CYCLE_R = crate::FieldReader<u32>;
7#[doc = "Field `ULP_CP_TIMER_SLP_CYCLE` writer - sleep cycles for ULP-coprocessor timer"]
8pub type ULP_CP_TIMER_SLP_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
9impl R {
10    #[doc = "Bits 8:31 - sleep cycles for ULP-coprocessor timer"]
11    #[inline(always)]
12    pub fn ulp_cp_timer_slp_cycle(&self) -> ULP_CP_TIMER_SLP_CYCLE_R {
13        ULP_CP_TIMER_SLP_CYCLE_R::new((self.bits >> 8) & 0x00ff_ffff)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("RTC_ULP_CP_TIMER_1")
20            .field("ulp_cp_timer_slp_cycle", &self.ulp_cp_timer_slp_cycle())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 8:31 - sleep cycles for ULP-coprocessor timer"]
26    #[inline(always)]
27    #[must_use]
28    pub fn ulp_cp_timer_slp_cycle(&mut self) -> ULP_CP_TIMER_SLP_CYCLE_W<RTC_ULP_CP_TIMER_1_SPEC> {
29        ULP_CP_TIMER_SLP_CYCLE_W::new(self, 8)
30    }
31}
32#[doc = "configure ulp sleep time\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_ulp_cp_timer_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_ulp_cp_timer_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
33pub struct RTC_ULP_CP_TIMER_1_SPEC;
34impl crate::RegisterSpec for RTC_ULP_CP_TIMER_1_SPEC {
35    type Ux = u32;
36}
37#[doc = "`read()` method returns [`rtc_ulp_cp_timer_1::R`](R) reader structure"]
38impl crate::Readable for RTC_ULP_CP_TIMER_1_SPEC {}
39#[doc = "`write(|w| ..)` method takes [`rtc_ulp_cp_timer_1::W`](W) writer structure"]
40impl crate::Writable for RTC_ULP_CP_TIMER_1_SPEC {
41    type Safety = crate::Unsafe;
42    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
44}
45#[doc = "`reset()` method sets RTC_ULP_CP_TIMER_1 to value 0xc800"]
46impl crate::Resettable for RTC_ULP_CP_TIMER_1_SPEC {
47    const RESET_VALUE: u32 = 0xc800;
48}
esp32s3_ulp/rtc_cntl/rtc_ulp_cp_timer_1.rs

esp32s3_ulp/rtc_cntl/
rtc_ulp_cp_timer_1.rs
