esp32s3_ulp/
rtc_cntl.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    _reserved0: [u8; 0xfc],
6    rtc_ulp_cp_timer: RTC_ULP_CP_TIMER,
7    rtc_ulp_cp_ctrl: RTC_ULP_CP_CTRL,
8    cocpu_ctrl: COCPU_CTRL,
9    _reserved3: [u8; 0x2c],
10    rtc_ulp_cp_timer_1: RTC_ULP_CP_TIMER_1,
11}
12impl RegisterBlock {
13    #[doc = "0xfc - configure ulp"]
14    #[inline(always)]
15    pub const fn rtc_ulp_cp_timer(&self) -> &RTC_ULP_CP_TIMER {
16        &self.rtc_ulp_cp_timer
17    }
18    #[doc = "0x100 - configure ulp"]
19    #[inline(always)]
20    pub const fn rtc_ulp_cp_ctrl(&self) -> &RTC_ULP_CP_CTRL {
21        &self.rtc_ulp_cp_ctrl
22    }
23    #[doc = "0x104 - configure ulp-riscv"]
24    #[inline(always)]
25    pub const fn cocpu_ctrl(&self) -> &COCPU_CTRL {
26        &self.cocpu_ctrl
27    }
28    #[doc = "0x134 - configure ulp sleep time"]
29    #[inline(always)]
30    pub const fn rtc_ulp_cp_timer_1(&self) -> &RTC_ULP_CP_TIMER_1 {
31        &self.rtc_ulp_cp_timer_1
32    }
33}
34#[doc = "RTC_ULP_CP_TIMER (rw) register accessor: configure ulp\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_ulp_cp_timer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_ulp_cp_timer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_ulp_cp_timer`] module"]
35pub type RTC_ULP_CP_TIMER = crate::Reg<rtc_ulp_cp_timer::RTC_ULP_CP_TIMER_SPEC>;
36#[doc = "configure ulp"]
37pub mod rtc_ulp_cp_timer;
38#[doc = "RTC_ULP_CP_CTRL (rw) register accessor: configure ulp\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_ulp_cp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_ulp_cp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_ulp_cp_ctrl`] module"]
39pub type RTC_ULP_CP_CTRL = crate::Reg<rtc_ulp_cp_ctrl::RTC_ULP_CP_CTRL_SPEC>;
40#[doc = "configure ulp"]
41pub mod rtc_ulp_cp_ctrl;
42#[doc = "COCPU_CTRL (rw) register accessor: configure ulp-riscv\n\nYou can [`read`](crate::Reg::read) this register and get [`cocpu_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cocpu_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cocpu_ctrl`] module"]
43pub type COCPU_CTRL = crate::Reg<cocpu_ctrl::COCPU_CTRL_SPEC>;
44#[doc = "configure ulp-riscv"]
45pub mod cocpu_ctrl;
46#[doc = "RTC_ULP_CP_TIMER_1 (rw) register accessor: configure ulp sleep time\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_ulp_cp_timer_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_ulp_cp_timer_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_ulp_cp_timer_1`] module"]
47pub type RTC_ULP_CP_TIMER_1 = crate::Reg<rtc_ulp_cp_timer_1::RTC_ULP_CP_TIMER_1_SPEC>;
48#[doc = "configure ulp sleep time"]
49pub mod rtc_ulp_cp_timer_1;
esp32s3_ulp/rtc_cntl.rs

esp32s3_ulp/
rtc_cntl.rs
