esp32s3_ulp/rtc_i2c/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `SDA_FORCE_OUT` reader - 1=push pull,0=open drain"]
6pub type SDA_FORCE_OUT_R = crate::BitReader;
7#[doc = "Field `SDA_FORCE_OUT` writer - 1=push pull,0=open drain"]
8pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCL_FORCE_OUT` reader - 1=push pull,0=open drain"]
10pub type SCL_FORCE_OUT_R = crate::BitReader;
11#[doc = "Field `SCL_FORCE_OUT` writer - 1=push pull,0=open drain"]
12pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MS_MODE` reader - 1=master,0=slave"]
14pub type MS_MODE_R = crate::BitReader;
15#[doc = "Field `MS_MODE` writer - 1=master,0=slave"]
16pub type MS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TRANS_START` reader - force start"]
18pub type TRANS_START_R = crate::BitReader;
19#[doc = "Field `TRANS_START` writer - force start"]
20pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TX_LSB_FIRST` reader - transit lsb first"]
22pub type TX_LSB_FIRST_R = crate::BitReader;
23#[doc = "Field `TX_LSB_FIRST` writer - transit lsb first"]
24pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RX_LSB_FIRST` reader - receive lsb first"]
26pub type RX_LSB_FIRST_R = crate::BitReader;
27#[doc = "Field `RX_LSB_FIRST` writer - receive lsb first"]
28pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `I2C_CTRL_CLK_GATE_EN` reader - configure i2c ctrl clk enable"]
30pub type I2C_CTRL_CLK_GATE_EN_R = crate::BitReader;
31#[doc = "Field `I2C_CTRL_CLK_GATE_EN` writer - configure i2c ctrl clk enable"]
32pub type I2C_CTRL_CLK_GATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `I2C_RESET` reader - rtc i2c sw reset"]
34pub type I2C_RESET_R = crate::BitReader;
35#[doc = "Field `I2C_RESET` writer - rtc i2c sw reset"]
36pub type I2C_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `I2CCLK_EN` reader - rtc i2c reg clk gating"]
38pub type I2CCLK_EN_R = crate::BitReader;
39#[doc = "Field `I2CCLK_EN` writer - rtc i2c reg clk gating"]
40pub type I2CCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bit 0 - 1=push pull,0=open drain"]
43    #[inline(always)]
44    pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
45        SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - 1=push pull,0=open drain"]
48    #[inline(always)]
49    pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
50        SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - 1=master,0=slave"]
53    #[inline(always)]
54    pub fn ms_mode(&self) -> MS_MODE_R {
55        MS_MODE_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - force start"]
58    #[inline(always)]
59    pub fn trans_start(&self) -> TRANS_START_R {
60        TRANS_START_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - transit lsb first"]
63    #[inline(always)]
64    pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
65        TX_LSB_FIRST_R::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 5 - receive lsb first"]
68    #[inline(always)]
69    pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
70        RX_LSB_FIRST_R::new(((self.bits >> 5) & 1) != 0)
71    }
72    #[doc = "Bit 29 - configure i2c ctrl clk enable"]
73    #[inline(always)]
74    pub fn i2c_ctrl_clk_gate_en(&self) -> I2C_CTRL_CLK_GATE_EN_R {
75        I2C_CTRL_CLK_GATE_EN_R::new(((self.bits >> 29) & 1) != 0)
76    }
77    #[doc = "Bit 30 - rtc i2c sw reset"]
78    #[inline(always)]
79    pub fn i2c_reset(&self) -> I2C_RESET_R {
80        I2C_RESET_R::new(((self.bits >> 30) & 1) != 0)
81    }
82    #[doc = "Bit 31 - rtc i2c reg clk gating"]
83    #[inline(always)]
84    pub fn i2cclk_en(&self) -> I2CCLK_EN_R {
85        I2CCLK_EN_R::new(((self.bits >> 31) & 1) != 0)
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("CTRL")
92            .field("sda_force_out", &self.sda_force_out())
93            .field("scl_force_out", &self.scl_force_out())
94            .field("ms_mode", &self.ms_mode())
95            .field("trans_start", &self.trans_start())
96            .field("tx_lsb_first", &self.tx_lsb_first())
97            .field("rx_lsb_first", &self.rx_lsb_first())
98            .field("i2c_ctrl_clk_gate_en", &self.i2c_ctrl_clk_gate_en())
99            .field("i2c_reset", &self.i2c_reset())
100            .field("i2cclk_en", &self.i2cclk_en())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bit 0 - 1=push pull,0=open drain"]
106    #[inline(always)]
107    #[must_use]
108    pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTRL_SPEC> {
109        SDA_FORCE_OUT_W::new(self, 0)
110    }
111    #[doc = "Bit 1 - 1=push pull,0=open drain"]
112    #[inline(always)]
113    #[must_use]
114    pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTRL_SPEC> {
115        SCL_FORCE_OUT_W::new(self, 1)
116    }
117    #[doc = "Bit 2 - 1=master,0=slave"]
118    #[inline(always)]
119    #[must_use]
120    pub fn ms_mode(&mut self) -> MS_MODE_W<CTRL_SPEC> {
121        MS_MODE_W::new(self, 2)
122    }
123    #[doc = "Bit 3 - force start"]
124    #[inline(always)]
125    #[must_use]
126    pub fn trans_start(&mut self) -> TRANS_START_W<CTRL_SPEC> {
127        TRANS_START_W::new(self, 3)
128    }
129    #[doc = "Bit 4 - transit lsb first"]
130    #[inline(always)]
131    #[must_use]
132    pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTRL_SPEC> {
133        TX_LSB_FIRST_W::new(self, 4)
134    }
135    #[doc = "Bit 5 - receive lsb first"]
136    #[inline(always)]
137    #[must_use]
138    pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTRL_SPEC> {
139        RX_LSB_FIRST_W::new(self, 5)
140    }
141    #[doc = "Bit 29 - configure i2c ctrl clk enable"]
142    #[inline(always)]
143    #[must_use]
144    pub fn i2c_ctrl_clk_gate_en(&mut self) -> I2C_CTRL_CLK_GATE_EN_W<CTRL_SPEC> {
145        I2C_CTRL_CLK_GATE_EN_W::new(self, 29)
146    }
147    #[doc = "Bit 30 - rtc i2c sw reset"]
148    #[inline(always)]
149    #[must_use]
150    pub fn i2c_reset(&mut self) -> I2C_RESET_W<CTRL_SPEC> {
151        I2C_RESET_W::new(self, 30)
152    }
153    #[doc = "Bit 31 - rtc i2c reg clk gating"]
154    #[inline(always)]
155    #[must_use]
156    pub fn i2cclk_en(&mut self) -> I2CCLK_EN_W<CTRL_SPEC> {
157        I2CCLK_EN_W::new(self, 31)
158    }
159}
160#[doc = "configure i2c ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
161pub struct CTRL_SPEC;
162impl crate::RegisterSpec for CTRL_SPEC {
163    type Ux = u32;
164}
165#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
166impl crate::Readable for CTRL_SPEC {}
167#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
168impl crate::Writable for CTRL_SPEC {
169    type Safety = crate::Unsafe;
170    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
171    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
172}
173#[doc = "`reset()` method sets CTRL to value 0"]
174impl crate::Resettable for CTRL_SPEC {
175    const RESET_VALUE: u32 = 0;
176}
esp32s3_ulp/rtc_i2c/ctrl.rs

esp32s3_ulp/rtc_i2c/
ctrl.rs
