Module esp32s3_hal::pac::extmem::icache_ctrl1

******* Description ***********

Structs

ICACHE_CTRL1_SPEC

******* Description ***********

R

Register ICACHE_CTRL1 reader

W

Register ICACHE_CTRL1 writer

Type Definitions

ICACHE_SHUT_CORE0_BUS_R

Field ICACHE_SHUT_CORE0_BUS reader - The bit is used to disable core0 ibus, 0: enable, 1: disable

ICACHE_SHUT_CORE0_BUS_W

Field ICACHE_SHUT_CORE0_BUS writer - The bit is used to disable core0 ibus, 0: enable, 1: disable

ICACHE_SHUT_CORE1_BUS_R

Field ICACHE_SHUT_CORE1_BUS reader - The bit is used to disable core1 ibus, 0: enable, 1: disable

ICACHE_SHUT_CORE1_BUS_W

Field ICACHE_SHUT_CORE1_BUS writer - The bit is used to disable core1 ibus, 0: enable, 1: disable