1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Field `RX_START` reader - This is the interrupt raw bit for UHCI_RX_START_INT interrupt. The interrupt is triggered when a separator has been sent."]
4pub type RX_START_R = crate::BitReader;
5#[doc = "Field `TX_START` reader - This is the interrupt raw bit for UHCI_TX_START_INT interrupt. The interrupt is triggered when DMA detects a separator."]
6pub type TX_START_R = crate::BitReader;
7#[doc = "Field `RX_HUNG` reader - This is the interrupt raw bit for UHCI_RX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to receive data than the configure value."]
8pub type RX_HUNG_R = crate::BitReader;
9#[doc = "Field `TX_HUNG` reader - This is the interrupt raw bit for UHCI_TX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to read data from RAM than the configured value."]
10pub type TX_HUNG_R = crate::BitReader;
11#[doc = "Field `IN_DONE` reader - This is the interrupt raw bit for UHCI_IN_DONE_INT interrupt. The interrupt is triggered when an receive descriptor is completed."]
12pub type IN_DONE_R = crate::BitReader;
13#[doc = "Field `IN_SUC_EOF` reader - This is the interrupt raw bit for UHCI_IN_SUC_EOF_INT interrupt. The interrupt is triggered when a data packet has been received successfully."]
14pub type IN_SUC_EOF_R = crate::BitReader;
15#[doc = "Field `IN_ERR_EOF` reader - This is the interrupt raw bit for UHCI_IN_ERR_EOF_INT interrupt. The interrupt is triggered when there are some errors in EOF in the receive descriptor."]
16pub type IN_ERR_EOF_R = crate::BitReader;
17#[doc = "Field `OUT_DONE` reader - This is the interrupt raw bit for UHCI_OUT_DONE_INT interrupt. The interrupt is triggered when an transmit descriptor is completed."]
18pub type OUT_DONE_R = crate::BitReader;
19#[doc = "Field `OUT_EOF` reader - This is the interrupt raw bit for UHCI_OUT_EOF_INT interrupt. The interrupt is triggered when the current descriptor's EOF bit is 1."]
20pub type OUT_EOF_R = crate::BitReader;
21#[doc = "Field `IN_DSCR_ERR` reader - This is the interrupt raw bit for UHCI_IN_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the receive descriptor."]
22pub type IN_DSCR_ERR_R = crate::BitReader;
23#[doc = "Field `OUT_DSCR_ERR` reader - This is the interrupt raw bit for UHCI_OUT_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the transmit descriptor."]
24pub type OUT_DSCR_ERR_R = crate::BitReader;
25#[doc = "Field `IN_DSCR_EMPTY` reader - This is the interrupt raw bit for UHCI_IN_DSCR_EMPTY_INT interrupt. The interrupt is triggered when there are not enough inlinks for DMA."]
26pub type IN_DSCR_EMPTY_R = crate::BitReader;
27#[doc = "Field `OUTLINK_EOF_ERR` reader - This is the interrupt raw bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. The interrupt is triggered when there are some errors in EOF in the transmit descriptor."]
28pub type OUTLINK_EOF_ERR_R = crate::BitReader;
29#[doc = "Field `OUT_TOTAL_EOF` reader - This is the interrupt raw bit for UHCI_OUT_TOTAL_EOF_INT interrupt. The interrupt is triggered when all data in the last buffer address has been sent out."]
30pub type OUT_TOTAL_EOF_R = crate::BitReader;
31#[doc = "Field `SEND_S_REG_Q` reader - This is the interrupt raw bit for UHCI_SEND_S_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using single_send mode."]
32pub type SEND_S_REG_Q_R = crate::BitReader;
33#[doc = "Field `SEND_A_REG_Q` reader - This is the interrupt raw bit for UHCI_SEND_A_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using always_send mode."]
34pub type SEND_A_REG_Q_R = crate::BitReader;
35#[doc = "Field `DMA_INFIFO_FULL_WM` reader - This is the interrupt raw bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. The interrupt is triggered when the number of data bytes in DMA RX FIFO has reached the configured threshold value."]
36pub type DMA_INFIFO_FULL_WM_R = crate::BitReader;
37impl R {
38 #[doc = "Bit 0 - This is the interrupt raw bit for UHCI_RX_START_INT interrupt. The interrupt is triggered when a separator has been sent."]
39 #[inline(always)]
40 pub fn rx_start(&self) -> RX_START_R {
41 RX_START_R::new((self.bits & 1) != 0)
42 }
43 #[doc = "Bit 1 - This is the interrupt raw bit for UHCI_TX_START_INT interrupt. The interrupt is triggered when DMA detects a separator."]
44 #[inline(always)]
45 pub fn tx_start(&self) -> TX_START_R {
46 TX_START_R::new(((self.bits >> 1) & 1) != 0)
47 }
48 #[doc = "Bit 2 - This is the interrupt raw bit for UHCI_RX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to receive data than the configure value."]
49 #[inline(always)]
50 pub fn rx_hung(&self) -> RX_HUNG_R {
51 RX_HUNG_R::new(((self.bits >> 2) & 1) != 0)
52 }
53 #[doc = "Bit 3 - This is the interrupt raw bit for UHCI_TX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to read data from RAM than the configured value."]
54 #[inline(always)]
55 pub fn tx_hung(&self) -> TX_HUNG_R {
56 TX_HUNG_R::new(((self.bits >> 3) & 1) != 0)
57 }
58 #[doc = "Bit 4 - This is the interrupt raw bit for UHCI_IN_DONE_INT interrupt. The interrupt is triggered when an receive descriptor is completed."]
59 #[inline(always)]
60 pub fn in_done(&self) -> IN_DONE_R {
61 IN_DONE_R::new(((self.bits >> 4) & 1) != 0)
62 }
63 #[doc = "Bit 5 - This is the interrupt raw bit for UHCI_IN_SUC_EOF_INT interrupt. The interrupt is triggered when a data packet has been received successfully."]
64 #[inline(always)]
65 pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
66 IN_SUC_EOF_R::new(((self.bits >> 5) & 1) != 0)
67 }
68 #[doc = "Bit 6 - This is the interrupt raw bit for UHCI_IN_ERR_EOF_INT interrupt. The interrupt is triggered when there are some errors in EOF in the receive descriptor."]
69 #[inline(always)]
70 pub fn in_err_eof(&self) -> IN_ERR_EOF_R {
71 IN_ERR_EOF_R::new(((self.bits >> 6) & 1) != 0)
72 }
73 #[doc = "Bit 7 - This is the interrupt raw bit for UHCI_OUT_DONE_INT interrupt. The interrupt is triggered when an transmit descriptor is completed."]
74 #[inline(always)]
75 pub fn out_done(&self) -> OUT_DONE_R {
76 OUT_DONE_R::new(((self.bits >> 7) & 1) != 0)
77 }
78 #[doc = "Bit 8 - This is the interrupt raw bit for UHCI_OUT_EOF_INT interrupt. The interrupt is triggered when the current descriptor's EOF bit is 1."]
79 #[inline(always)]
80 pub fn out_eof(&self) -> OUT_EOF_R {
81 OUT_EOF_R::new(((self.bits >> 8) & 1) != 0)
82 }
83 #[doc = "Bit 9 - This is the interrupt raw bit for UHCI_IN_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the receive descriptor."]
84 #[inline(always)]
85 pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R {
86 IN_DSCR_ERR_R::new(((self.bits >> 9) & 1) != 0)
87 }
88 #[doc = "Bit 10 - This is the interrupt raw bit for UHCI_OUT_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the transmit descriptor."]
89 #[inline(always)]
90 pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R {
91 OUT_DSCR_ERR_R::new(((self.bits >> 10) & 1) != 0)
92 }
93 #[doc = "Bit 11 - This is the interrupt raw bit for UHCI_IN_DSCR_EMPTY_INT interrupt. The interrupt is triggered when there are not enough inlinks for DMA."]
94 #[inline(always)]
95 pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R {
96 IN_DSCR_EMPTY_R::new(((self.bits >> 11) & 1) != 0)
97 }
98 #[doc = "Bit 12 - This is the interrupt raw bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. The interrupt is triggered when there are some errors in EOF in the transmit descriptor."]
99 #[inline(always)]
100 pub fn outlink_eof_err(&self) -> OUTLINK_EOF_ERR_R {
101 OUTLINK_EOF_ERR_R::new(((self.bits >> 12) & 1) != 0)
102 }
103 #[doc = "Bit 13 - This is the interrupt raw bit for UHCI_OUT_TOTAL_EOF_INT interrupt. The interrupt is triggered when all data in the last buffer address has been sent out."]
104 #[inline(always)]
105 pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R {
106 OUT_TOTAL_EOF_R::new(((self.bits >> 13) & 1) != 0)
107 }
108 #[doc = "Bit 14 - This is the interrupt raw bit for UHCI_SEND_S_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using single_send mode."]
109 #[inline(always)]
110 pub fn send_s_reg_q(&self) -> SEND_S_REG_Q_R {
111 SEND_S_REG_Q_R::new(((self.bits >> 14) & 1) != 0)
112 }
113 #[doc = "Bit 15 - This is the interrupt raw bit for UHCI_SEND_A_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using always_send mode."]
114 #[inline(always)]
115 pub fn send_a_reg_q(&self) -> SEND_A_REG_Q_R {
116 SEND_A_REG_Q_R::new(((self.bits >> 15) & 1) != 0)
117 }
118 #[doc = "Bit 16 - This is the interrupt raw bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. The interrupt is triggered when the number of data bytes in DMA RX FIFO has reached the configured threshold value."]
119 #[inline(always)]
120 pub fn dma_infifo_full_wm(&self) -> DMA_INFIFO_FULL_WM_R {
121 DMA_INFIFO_FULL_WM_R::new(((self.bits >> 16) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("INT_RAW")
128 .field("rx_start", &self.rx_start())
129 .field("tx_start", &self.tx_start())
130 .field("rx_hung", &self.rx_hung())
131 .field("tx_hung", &self.tx_hung())
132 .field("in_done", &self.in_done())
133 .field("in_suc_eof", &self.in_suc_eof())
134 .field("in_err_eof", &self.in_err_eof())
135 .field("out_done", &self.out_done())
136 .field("out_eof", &self.out_eof())
137 .field("in_dscr_err", &self.in_dscr_err())
138 .field("out_dscr_err", &self.out_dscr_err())
139 .field("in_dscr_empty", &self.in_dscr_empty())
140 .field("outlink_eof_err", &self.outlink_eof_err())
141 .field("out_total_eof", &self.out_total_eof())
142 .field("send_s_reg_q", &self.send_s_reg_q())
143 .field("send_a_reg_q", &self.send_a_reg_q())
144 .field("dma_infifo_full_wm", &self.dma_infifo_full_wm())
145 .finish()
146 }
147}
148#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
149pub struct INT_RAW_SPEC;
150impl crate::RegisterSpec for INT_RAW_SPEC {
151 type Ux = u32;
152}
153#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
154impl crate::Readable for INT_RAW_SPEC {}
155#[doc = "`reset()` method sets INT_RAW to value 0"]
156impl crate::Resettable for INT_RAW_SPEC {
157 const RESET_VALUE: u32 = 0;
158}