1#[doc = "Register `MISC` reader"]
2pub type R = crate::R<MISC_SPEC>;
3#[doc = "Register `MISC` writer"]
4pub type W = crate::W<MISC_SPEC>;
5#[doc = "Field `CS_DIS(0-5)` reader - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
6pub type CS_DIS_R = crate::BitReader;
7#[doc = "Field `CS_DIS(0-5)` writer - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
8pub type CS_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CK_DIS` reader - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
10pub type CK_DIS_R = crate::BitReader;
11#[doc = "Field `CK_DIS` writer - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
12pub type CK_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MASTER_CS_POL` reader - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state."]
14pub type MASTER_CS_POL_R = crate::FieldReader;
15#[doc = "Field `MASTER_CS_POL` writer - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state."]
16pub type MASTER_CS_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `CLK_DATA_DTR_EN` reader - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
18pub type CLK_DATA_DTR_EN_R = crate::BitReader;
19#[doc = "Field `CLK_DATA_DTR_EN` writer - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
20pub type CLK_DATA_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DATA_DTR_EN` reader - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
22pub type DATA_DTR_EN_R = crate::BitReader;
23#[doc = "Field `DATA_DTR_EN` writer - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
24pub type DATA_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ADDR_DTR_EN` reader - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
26pub type ADDR_DTR_EN_R = crate::BitReader;
27#[doc = "Field `ADDR_DTR_EN` writer - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
28pub type ADDR_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CMD_DTR_EN` reader - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
30pub type CMD_DTR_EN_R = crate::BitReader;
31#[doc = "Field `CMD_DTR_EN` writer - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
32pub type CMD_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CD_DATA_SET` reader - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
34pub type CD_DATA_SET_R = crate::BitReader;
35#[doc = "Field `CD_DATA_SET` writer - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
36pub type CD_DATA_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CD_DUMMY_SET` reader - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DUMMY state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
38pub type CD_DUMMY_SET_R = crate::BitReader;
39#[doc = "Field `CD_DUMMY_SET` writer - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DUMMY state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
40pub type CD_DUMMY_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CD_ADDR_SET` reader - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_ADDR state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
42pub type CD_ADDR_SET_R = crate::BitReader;
43#[doc = "Field `CD_ADDR_SET` writer - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_ADDR state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
44pub type CD_ADDR_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SLAVE_CS_POL` reader - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
46pub type SLAVE_CS_POL_R = crate::BitReader;
47#[doc = "Field `SLAVE_CS_POL` writer - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
48pub type SLAVE_CS_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `DQS_IDLE_EDGE` reader - The default value of spi_dqs. Can be configured in CONF state."]
50pub type DQS_IDLE_EDGE_R = crate::BitReader;
51#[doc = "Field `DQS_IDLE_EDGE` writer - The default value of spi_dqs. Can be configured in CONF state."]
52pub type DQS_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `CD_CMD_SET` reader - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_CMD state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
54pub type CD_CMD_SET_R = crate::BitReader;
55#[doc = "Field `CD_CMD_SET` writer - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_CMD state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
56pub type CD_CMD_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `CD_IDLE_EDGE` reader - The default value of spi_cd. Can be configured in CONF state."]
58pub type CD_IDLE_EDGE_R = crate::BitReader;
59#[doc = "Field `CD_IDLE_EDGE` writer - The default value of spi_cd. Can be configured in CONF state."]
60pub type CD_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
62pub type CK_IDLE_EDGE_R = crate::BitReader;
63#[doc = "Field `CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
64pub type CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `CS_KEEP_ACTIVE` reader - spi cs line keep low when the bit is set. Can be configured in CONF state."]
66pub type CS_KEEP_ACTIVE_R = crate::BitReader;
67#[doc = "Field `CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set. Can be configured in CONF state."]
68pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `QUAD_DIN_PIN_SWAP` reader - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
70pub type QUAD_DIN_PIN_SWAP_R = crate::BitReader;
71#[doc = "Field `QUAD_DIN_PIN_SWAP` writer - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
72pub type QUAD_DIN_PIN_SWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
73impl R {
74 #[doc = "Set this bit to raise high SPI_CS(0-5) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-5) is in low level when SPI1 transfer starts"]
75 #[doc = ""]
76 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
77 #[inline(always)]
78 pub fn cs_dis(&self, n: u8) -> CS_DIS_R {
79 #[allow(clippy::no_effect)]
80 [(); 6][n as usize];
81 CS_DIS_R::new(((self.bits >> n) & 1) != 0)
82 }
83 #[doc = "Iterator for array of:"]
84 #[doc = "Set this bit to raise high SPI_CS(0-5) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-5) is in low level when SPI1 transfer starts"]
85 #[inline(always)]
86 pub fn cs_dis_iter(&self) -> impl Iterator<Item = CS_DIS_R> + '_ {
87 (0..6).map(move |n| CS_DIS_R::new(((self.bits >> n) & 1) != 0))
88 }
89 #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
90 #[inline(always)]
91 pub fn cs0_dis(&self) -> CS_DIS_R {
92 CS_DIS_R::new((self.bits & 1) != 0)
93 }
94 #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
95 #[inline(always)]
96 pub fn cs1_dis(&self) -> CS_DIS_R {
97 CS_DIS_R::new(((self.bits >> 1) & 1) != 0)
98 }
99 #[doc = "Bit 2 - Set this bit to raise high SPI_CS2 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS2 is in low level when SPI1 transfer starts"]
100 #[inline(always)]
101 pub fn cs2_dis(&self) -> CS_DIS_R {
102 CS_DIS_R::new(((self.bits >> 2) & 1) != 0)
103 }
104 #[doc = "Bit 3 - Set this bit to raise high SPI_CS3 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS3 is in low level when SPI1 transfer starts"]
105 #[inline(always)]
106 pub fn cs3_dis(&self) -> CS_DIS_R {
107 CS_DIS_R::new(((self.bits >> 3) & 1) != 0)
108 }
109 #[doc = "Bit 4 - Set this bit to raise high SPI_CS4 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS4 is in low level when SPI1 transfer starts"]
110 #[inline(always)]
111 pub fn cs4_dis(&self) -> CS_DIS_R {
112 CS_DIS_R::new(((self.bits >> 4) & 1) != 0)
113 }
114 #[doc = "Bit 5 - Set this bit to raise high SPI_CS5 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS5 is in low level when SPI1 transfer starts"]
115 #[inline(always)]
116 pub fn cs5_dis(&self) -> CS_DIS_R {
117 CS_DIS_R::new(((self.bits >> 5) & 1) != 0)
118 }
119 #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
120 #[inline(always)]
121 pub fn ck_dis(&self) -> CK_DIS_R {
122 CK_DIS_R::new(((self.bits >> 6) & 1) != 0)
123 }
124 #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state."]
125 #[inline(always)]
126 pub fn master_cs_pol(&self) -> MASTER_CS_POL_R {
127 MASTER_CS_POL_R::new(((self.bits >> 7) & 0x3f) as u8)
128 }
129 #[doc = "Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
130 #[inline(always)]
131 pub fn clk_data_dtr_en(&self) -> CLK_DATA_DTR_EN_R {
132 CLK_DATA_DTR_EN_R::new(((self.bits >> 16) & 1) != 0)
133 }
134 #[doc = "Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
135 #[inline(always)]
136 pub fn data_dtr_en(&self) -> DATA_DTR_EN_R {
137 DATA_DTR_EN_R::new(((self.bits >> 17) & 1) != 0)
138 }
139 #[doc = "Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
140 #[inline(always)]
141 pub fn addr_dtr_en(&self) -> ADDR_DTR_EN_R {
142 ADDR_DTR_EN_R::new(((self.bits >> 18) & 1) != 0)
143 }
144 #[doc = "Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
145 #[inline(always)]
146 pub fn cmd_dtr_en(&self) -> CMD_DTR_EN_R {
147 CMD_DTR_EN_R::new(((self.bits >> 19) & 1) != 0)
148 }
149 #[doc = "Bit 20 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
150 #[inline(always)]
151 pub fn cd_data_set(&self) -> CD_DATA_SET_R {
152 CD_DATA_SET_R::new(((self.bits >> 20) & 1) != 0)
153 }
154 #[doc = "Bit 21 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DUMMY state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
155 #[inline(always)]
156 pub fn cd_dummy_set(&self) -> CD_DUMMY_SET_R {
157 CD_DUMMY_SET_R::new(((self.bits >> 21) & 1) != 0)
158 }
159 #[doc = "Bit 22 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_ADDR state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
160 #[inline(always)]
161 pub fn cd_addr_set(&self) -> CD_ADDR_SET_R {
162 CD_ADDR_SET_R::new(((self.bits >> 22) & 1) != 0)
163 }
164 #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
165 #[inline(always)]
166 pub fn slave_cs_pol(&self) -> SLAVE_CS_POL_R {
167 SLAVE_CS_POL_R::new(((self.bits >> 23) & 1) != 0)
168 }
169 #[doc = "Bit 24 - The default value of spi_dqs. Can be configured in CONF state."]
170 #[inline(always)]
171 pub fn dqs_idle_edge(&self) -> DQS_IDLE_EDGE_R {
172 DQS_IDLE_EDGE_R::new(((self.bits >> 24) & 1) != 0)
173 }
174 #[doc = "Bit 25 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_CMD state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
175 #[inline(always)]
176 pub fn cd_cmd_set(&self) -> CD_CMD_SET_R {
177 CD_CMD_SET_R::new(((self.bits >> 25) & 1) != 0)
178 }
179 #[doc = "Bit 26 - The default value of spi_cd. Can be configured in CONF state."]
180 #[inline(always)]
181 pub fn cd_idle_edge(&self) -> CD_IDLE_EDGE_R {
182 CD_IDLE_EDGE_R::new(((self.bits >> 26) & 1) != 0)
183 }
184 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
185 #[inline(always)]
186 pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R {
187 CK_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0)
188 }
189 #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
190 #[inline(always)]
191 pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R {
192 CS_KEEP_ACTIVE_R::new(((self.bits >> 30) & 1) != 0)
193 }
194 #[doc = "Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
195 #[inline(always)]
196 pub fn quad_din_pin_swap(&self) -> QUAD_DIN_PIN_SWAP_R {
197 QUAD_DIN_PIN_SWAP_R::new(((self.bits >> 31) & 1) != 0)
198 }
199}
200#[cfg(feature = "impl-register-debug")]
201impl core::fmt::Debug for R {
202 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
203 f.debug_struct("MISC")
204 .field("ck_dis", &self.ck_dis())
205 .field("master_cs_pol", &self.master_cs_pol())
206 .field("clk_data_dtr_en", &self.clk_data_dtr_en())
207 .field("data_dtr_en", &self.data_dtr_en())
208 .field("addr_dtr_en", &self.addr_dtr_en())
209 .field("cmd_dtr_en", &self.cmd_dtr_en())
210 .field("cd_data_set", &self.cd_data_set())
211 .field("cd_dummy_set", &self.cd_dummy_set())
212 .field("cd_addr_set", &self.cd_addr_set())
213 .field("slave_cs_pol", &self.slave_cs_pol())
214 .field("dqs_idle_edge", &self.dqs_idle_edge())
215 .field("cd_cmd_set", &self.cd_cmd_set())
216 .field("cd_idle_edge", &self.cd_idle_edge())
217 .field("ck_idle_edge", &self.ck_idle_edge())
218 .field("cs_keep_active", &self.cs_keep_active())
219 .field("quad_din_pin_swap", &self.quad_din_pin_swap())
220 .field("cs0_dis", &self.cs0_dis())
221 .field("cs1_dis", &self.cs1_dis())
222 .field("cs2_dis", &self.cs2_dis())
223 .field("cs3_dis", &self.cs3_dis())
224 .field("cs4_dis", &self.cs4_dis())
225 .field("cs5_dis", &self.cs5_dis())
226 .finish()
227 }
228}
229impl W {
230 #[doc = "Set this bit to raise high SPI_CS(0-5) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-5) is in low level when SPI1 transfer starts"]
231 #[doc = ""]
232 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
233 #[inline(always)]
234 pub fn cs_dis(&mut self, n: u8) -> CS_DIS_W<MISC_SPEC> {
235 #[allow(clippy::no_effect)]
236 [(); 6][n as usize];
237 CS_DIS_W::new(self, n)
238 }
239 #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
240 #[inline(always)]
241 pub fn cs0_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
242 CS_DIS_W::new(self, 0)
243 }
244 #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
245 #[inline(always)]
246 pub fn cs1_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
247 CS_DIS_W::new(self, 1)
248 }
249 #[doc = "Bit 2 - Set this bit to raise high SPI_CS2 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS2 is in low level when SPI1 transfer starts"]
250 #[inline(always)]
251 pub fn cs2_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
252 CS_DIS_W::new(self, 2)
253 }
254 #[doc = "Bit 3 - Set this bit to raise high SPI_CS3 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS3 is in low level when SPI1 transfer starts"]
255 #[inline(always)]
256 pub fn cs3_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
257 CS_DIS_W::new(self, 3)
258 }
259 #[doc = "Bit 4 - Set this bit to raise high SPI_CS4 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS4 is in low level when SPI1 transfer starts"]
260 #[inline(always)]
261 pub fn cs4_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
262 CS_DIS_W::new(self, 4)
263 }
264 #[doc = "Bit 5 - Set this bit to raise high SPI_CS5 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS5 is in low level when SPI1 transfer starts"]
265 #[inline(always)]
266 pub fn cs5_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
267 CS_DIS_W::new(self, 5)
268 }
269 #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
270 #[inline(always)]
271 pub fn ck_dis(&mut self) -> CK_DIS_W<MISC_SPEC> {
272 CK_DIS_W::new(self, 6)
273 }
274 #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state."]
275 #[inline(always)]
276 pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<MISC_SPEC> {
277 MASTER_CS_POL_W::new(self, 7)
278 }
279 #[doc = "Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
280 #[inline(always)]
281 pub fn clk_data_dtr_en(&mut self) -> CLK_DATA_DTR_EN_W<MISC_SPEC> {
282 CLK_DATA_DTR_EN_W::new(self, 16)
283 }
284 #[doc = "Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
285 #[inline(always)]
286 pub fn data_dtr_en(&mut self) -> DATA_DTR_EN_W<MISC_SPEC> {
287 DATA_DTR_EN_W::new(self, 17)
288 }
289 #[doc = "Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
290 #[inline(always)]
291 pub fn addr_dtr_en(&mut self) -> ADDR_DTR_EN_W<MISC_SPEC> {
292 ADDR_DTR_EN_W::new(self, 18)
293 }
294 #[doc = "Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
295 #[inline(always)]
296 pub fn cmd_dtr_en(&mut self) -> CMD_DTR_EN_W<MISC_SPEC> {
297 CMD_DTR_EN_W::new(self, 19)
298 }
299 #[doc = "Bit 20 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
300 #[inline(always)]
301 pub fn cd_data_set(&mut self) -> CD_DATA_SET_W<MISC_SPEC> {
302 CD_DATA_SET_W::new(self, 20)
303 }
304 #[doc = "Bit 21 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_DUMMY state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
305 #[inline(always)]
306 pub fn cd_dummy_set(&mut self) -> CD_DUMMY_SET_W<MISC_SPEC> {
307 CD_DUMMY_SET_W::new(self, 21)
308 }
309 #[doc = "Bit 22 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_ADDR state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
310 #[inline(always)]
311 pub fn cd_addr_set(&mut self) -> CD_ADDR_SET_W<MISC_SPEC> {
312 CD_ADDR_SET_W::new(self, 22)
313 }
314 #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
315 #[inline(always)]
316 pub fn slave_cs_pol(&mut self) -> SLAVE_CS_POL_W<MISC_SPEC> {
317 SLAVE_CS_POL_W::new(self, 23)
318 }
319 #[doc = "Bit 24 - The default value of spi_dqs. Can be configured in CONF state."]
320 #[inline(always)]
321 pub fn dqs_idle_edge(&mut self) -> DQS_IDLE_EDGE_W<MISC_SPEC> {
322 DQS_IDLE_EDGE_W::new(self, 24)
323 }
324 #[doc = "Bit 25 - 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST\\[3:0\\] is in SPI_SEND_CMD state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state."]
325 #[inline(always)]
326 pub fn cd_cmd_set(&mut self) -> CD_CMD_SET_W<MISC_SPEC> {
327 CD_CMD_SET_W::new(self, 25)
328 }
329 #[doc = "Bit 26 - The default value of spi_cd. Can be configured in CONF state."]
330 #[inline(always)]
331 pub fn cd_idle_edge(&mut self) -> CD_IDLE_EDGE_W<MISC_SPEC> {
332 CD_IDLE_EDGE_W::new(self, 26)
333 }
334 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
335 #[inline(always)]
336 pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
337 CK_IDLE_EDGE_W::new(self, 29)
338 }
339 #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
340 #[inline(always)]
341 pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
342 CS_KEEP_ACTIVE_W::new(self, 30)
343 }
344 #[doc = "Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."]
345 #[inline(always)]
346 pub fn quad_din_pin_swap(&mut self) -> QUAD_DIN_PIN_SWAP_W<MISC_SPEC> {
347 QUAD_DIN_PIN_SWAP_W::new(self, 31)
348 }
349}
350#[doc = "SPI misc register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
351pub struct MISC_SPEC;
352impl crate::RegisterSpec for MISC_SPEC {
353 type Ux = u32;
354}
355#[doc = "`read()` method returns [`misc::R`](R) reader structure"]
356impl crate::Readable for MISC_SPEC {}
357#[doc = "`write(|w| ..)` method takes [`misc::W`](W) writer structure"]
358impl crate::Writable for MISC_SPEC {
359 type Safety = crate::Unsafe;
360}
361#[doc = "`reset()` method sets MISC to value 0x3e"]
362impl crate::Resettable for MISC_SPEC {
363 const RESET_VALUE: u32 = 0x3e;
364}