1#![doc = "Peripheral access API for ESP32-S2 microcontrollers (generated using svd2rust v0.36.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
2#![allow(non_camel_case_types)]
3#![allow(non_snake_case)]
4#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
5#![no_std]
6#![cfg_attr(docsrs, feature(doc_auto_cfg))]
7#[doc = r"Number available in the NVIC for configuring priority"]
8pub const NVIC_PRIO_BITS: u8 = 0;
9#[allow(unused_imports)]
10use generic::*;
11#[doc = r"Common register and bit access and modify traits"]
12pub mod generic;
13#[cfg(feature = "rt")]
14extern "C" {
15 fn WIFI_MAC();
16 fn WIFI_NMI();
17 fn WIFI_PWR();
18 fn WIFI_BB();
19 fn BT_MAC();
20 fn BT_BB();
21 fn BT_BB_NMI();
22 fn RWBT();
23 fn RWBLE();
24 fn RWBT_NMI();
25 fn RWBLE_NMI();
26 fn SLC0();
27 fn SLC1();
28 fn UHCI0();
29 fn UHCI1();
30 fn TG0_T0_LEVEL();
31 fn TG0_T1_LEVEL();
32 fn TG0_WDT_LEVEL();
33 fn TG0_LACT_LEVEL();
34 fn TG1_T0_LEVEL();
35 fn TG1_T1_LEVEL();
36 fn TG1_WDT_LEVEL();
37 fn TG1_LACT_LEVEL();
38 fn GPIO();
39 fn GPIO_NMI();
40 fn GPIO_INTR_2();
41 fn GPIO_NMI_2();
42 fn DEDICATED_GPIO();
43 fn FROM_CPU_INTR0();
44 fn FROM_CPU_INTR1();
45 fn FROM_CPU_INTR2();
46 fn FROM_CPU_INTR3();
47 fn SPI1();
48 fn SPI2();
49 fn SPI3();
50 fn I2S0();
51 fn I2S1();
52 fn UART0();
53 fn UART1();
54 fn UART2();
55 fn SDIO_HOST();
56 fn LEDC();
57 fn EFUSE();
58 fn TWAI0();
59 fn USB();
60 fn RTC_CORE();
61 fn RMT();
62 fn PCNT();
63 fn I2C_EXT0();
64 fn I2C_EXT1();
65 fn RSA();
66 fn SHA();
67 fn AES();
68 fn SPI2_DMA();
69 fn SPI3_DMA();
70 fn WDT();
71 fn TIMER1();
72 fn TIMER2();
73 fn TG0_T0_EDGE();
74 fn TG0_T1_EDGE();
75 fn TG0_WDT_EDGE();
76 fn TG0_LACT_EDGE();
77 fn TG1_T0_EDGE();
78 fn TG1_T1_EDGE();
79 fn TG1_WDT_EDGE();
80 fn TG1_LACT_EDGE();
81 fn CACHE_IA();
82 fn SYSTIMER_TARGET0();
83 fn SYSTIMER_TARGET1();
84 fn SYSTIMER_TARGET2();
85 fn PMS_PRO_IRAM0_ILG();
86 fn PMS_PRO_DRAM0_ILG();
87 fn PMS_PRO_DPORT_ILG();
88 fn PMS_PRO_AHB_ILG();
89 fn PMS_PRO_CACHE_ILG();
90 fn PMS_DMA_APB_I_ILG();
91 fn PMS_DMA_RX_I_ILG();
92 fn PMS_DMA_TX_I_ILG();
93 fn SPI0_REJECT_CACHE();
94 fn DMA_COPY();
95 fn SPI4_DMA();
96 fn SPI4();
97 fn ICACHE_PRELOAD();
98 fn DCACHE_PRELOAD();
99 fn APB_ADC();
100 fn CRYPTO_DMA();
101 fn CPU_PERI_ERR();
102 fn APB_PERI_ERR();
103 fn DCACHE_SYNC();
104 fn ICACHE_SYNC();
105}
106#[doc(hidden)]
107#[repr(C)]
108pub union Vector {
109 pub _handler: unsafe extern "C" fn(),
110 _reserved: u32,
111}
112#[cfg(feature = "rt")]
113#[link_section = ".rwtext"]
114#[doc(hidden)]
115pub static __INTERRUPTS: [Vector; 95] = [
116 Vector { _handler: WIFI_MAC },
117 Vector { _handler: WIFI_NMI },
118 Vector { _handler: WIFI_PWR },
119 Vector { _handler: WIFI_BB },
120 Vector { _handler: BT_MAC },
121 Vector { _handler: BT_BB },
122 Vector {
123 _handler: BT_BB_NMI,
124 },
125 Vector { _handler: RWBT },
126 Vector { _handler: RWBLE },
127 Vector { _handler: RWBT_NMI },
128 Vector {
129 _handler: RWBLE_NMI,
130 },
131 Vector { _handler: SLC0 },
132 Vector { _handler: SLC1 },
133 Vector { _handler: UHCI0 },
134 Vector { _handler: UHCI1 },
135 Vector {
136 _handler: TG0_T0_LEVEL,
137 },
138 Vector {
139 _handler: TG0_T1_LEVEL,
140 },
141 Vector {
142 _handler: TG0_WDT_LEVEL,
143 },
144 Vector {
145 _handler: TG0_LACT_LEVEL,
146 },
147 Vector {
148 _handler: TG1_T0_LEVEL,
149 },
150 Vector {
151 _handler: TG1_T1_LEVEL,
152 },
153 Vector {
154 _handler: TG1_WDT_LEVEL,
155 },
156 Vector {
157 _handler: TG1_LACT_LEVEL,
158 },
159 Vector { _handler: GPIO },
160 Vector { _handler: GPIO_NMI },
161 Vector {
162 _handler: GPIO_INTR_2,
163 },
164 Vector {
165 _handler: GPIO_NMI_2,
166 },
167 Vector {
168 _handler: DEDICATED_GPIO,
169 },
170 Vector {
171 _handler: FROM_CPU_INTR0,
172 },
173 Vector {
174 _handler: FROM_CPU_INTR1,
175 },
176 Vector {
177 _handler: FROM_CPU_INTR2,
178 },
179 Vector {
180 _handler: FROM_CPU_INTR3,
181 },
182 Vector { _handler: SPI1 },
183 Vector { _handler: SPI2 },
184 Vector { _handler: SPI3 },
185 Vector { _handler: I2S0 },
186 Vector { _handler: I2S1 },
187 Vector { _handler: UART0 },
188 Vector { _handler: UART1 },
189 Vector { _handler: UART2 },
190 Vector {
191 _handler: SDIO_HOST,
192 },
193 Vector { _reserved: 0 },
194 Vector { _reserved: 0 },
195 Vector { _reserved: 0 },
196 Vector { _reserved: 0 },
197 Vector { _handler: LEDC },
198 Vector { _handler: EFUSE },
199 Vector { _handler: TWAI0 },
200 Vector { _handler: USB },
201 Vector { _handler: RTC_CORE },
202 Vector { _handler: RMT },
203 Vector { _handler: PCNT },
204 Vector { _handler: I2C_EXT0 },
205 Vector { _handler: I2C_EXT1 },
206 Vector { _handler: RSA },
207 Vector { _handler: SHA },
208 Vector { _handler: AES },
209 Vector { _handler: SPI2_DMA },
210 Vector { _handler: SPI3_DMA },
211 Vector { _handler: WDT },
212 Vector { _handler: TIMER1 },
213 Vector { _handler: TIMER2 },
214 Vector {
215 _handler: TG0_T0_EDGE,
216 },
217 Vector {
218 _handler: TG0_T1_EDGE,
219 },
220 Vector {
221 _handler: TG0_WDT_EDGE,
222 },
223 Vector {
224 _handler: TG0_LACT_EDGE,
225 },
226 Vector {
227 _handler: TG1_T0_EDGE,
228 },
229 Vector {
230 _handler: TG1_T1_EDGE,
231 },
232 Vector {
233 _handler: TG1_WDT_EDGE,
234 },
235 Vector {
236 _handler: TG1_LACT_EDGE,
237 },
238 Vector { _handler: CACHE_IA },
239 Vector {
240 _handler: SYSTIMER_TARGET0,
241 },
242 Vector {
243 _handler: SYSTIMER_TARGET1,
244 },
245 Vector {
246 _handler: SYSTIMER_TARGET2,
247 },
248 Vector { _reserved: 0 },
249 Vector {
250 _handler: PMS_PRO_IRAM0_ILG,
251 },
252 Vector {
253 _handler: PMS_PRO_DRAM0_ILG,
254 },
255 Vector {
256 _handler: PMS_PRO_DPORT_ILG,
257 },
258 Vector {
259 _handler: PMS_PRO_AHB_ILG,
260 },
261 Vector {
262 _handler: PMS_PRO_CACHE_ILG,
263 },
264 Vector {
265 _handler: PMS_DMA_APB_I_ILG,
266 },
267 Vector {
268 _handler: PMS_DMA_RX_I_ILG,
269 },
270 Vector {
271 _handler: PMS_DMA_TX_I_ILG,
272 },
273 Vector {
274 _handler: SPI0_REJECT_CACHE,
275 },
276 Vector { _handler: DMA_COPY },
277 Vector { _handler: SPI4_DMA },
278 Vector { _handler: SPI4 },
279 Vector {
280 _handler: ICACHE_PRELOAD,
281 },
282 Vector {
283 _handler: DCACHE_PRELOAD,
284 },
285 Vector { _handler: APB_ADC },
286 Vector {
287 _handler: CRYPTO_DMA,
288 },
289 Vector {
290 _handler: CPU_PERI_ERR,
291 },
292 Vector {
293 _handler: APB_PERI_ERR,
294 },
295 Vector {
296 _handler: DCACHE_SYNC,
297 },
298 Vector {
299 _handler: ICACHE_SYNC,
300 },
301];
302#[doc = r"Enumeration of all the interrupts."]
303#[cfg_attr(feature = "defmt", derive(defmt::Format))]
304#[derive(Copy, Clone, Debug, PartialEq, Eq)]
305#[repr(u16)]
306pub enum Interrupt {
307 #[doc = "0 - WIFI_MAC"]
308 WIFI_MAC = 0,
309 #[doc = "1 - WIFI_NMI"]
310 WIFI_NMI = 1,
311 #[doc = "2 - WIFI_PWR"]
312 WIFI_PWR = 2,
313 #[doc = "3 - WIFI_BB"]
314 WIFI_BB = 3,
315 #[doc = "4 - BT_MAC"]
316 BT_MAC = 4,
317 #[doc = "5 - BT_BB"]
318 BT_BB = 5,
319 #[doc = "6 - BT_BB_NMI"]
320 BT_BB_NMI = 6,
321 #[doc = "7 - RWBT"]
322 RWBT = 7,
323 #[doc = "8 - RWBLE"]
324 RWBLE = 8,
325 #[doc = "9 - RWBT_NMI"]
326 RWBT_NMI = 9,
327 #[doc = "10 - RWBLE_NMI"]
328 RWBLE_NMI = 10,
329 #[doc = "11 - SLC0"]
330 SLC0 = 11,
331 #[doc = "12 - SLC1"]
332 SLC1 = 12,
333 #[doc = "13 - UHCI0"]
334 UHCI0 = 13,
335 #[doc = "14 - UHCI1"]
336 UHCI1 = 14,
337 #[doc = "15 - TG0_T0_LEVEL"]
338 TG0_T0_LEVEL = 15,
339 #[doc = "16 - TG0_T1_LEVEL"]
340 TG0_T1_LEVEL = 16,
341 #[doc = "17 - TG0_WDT_LEVEL"]
342 TG0_WDT_LEVEL = 17,
343 #[doc = "18 - TG0_LACT_LEVEL"]
344 TG0_LACT_LEVEL = 18,
345 #[doc = "19 - TG1_T0_LEVEL"]
346 TG1_T0_LEVEL = 19,
347 #[doc = "20 - TG1_T1_LEVEL"]
348 TG1_T1_LEVEL = 20,
349 #[doc = "21 - TG1_WDT_LEVEL"]
350 TG1_WDT_LEVEL = 21,
351 #[doc = "22 - TG1_LACT_LEVEL"]
352 TG1_LACT_LEVEL = 22,
353 #[doc = "23 - GPIO"]
354 GPIO = 23,
355 #[doc = "24 - GPIO_NMI"]
356 GPIO_NMI = 24,
357 #[doc = "25 - GPIO_INTR_2"]
358 GPIO_INTR_2 = 25,
359 #[doc = "26 - GPIO_NMI_2"]
360 GPIO_NMI_2 = 26,
361 #[doc = "27 - DEDICATED_GPIO"]
362 DEDICATED_GPIO = 27,
363 #[doc = "28 - FROM_CPU_INTR0"]
364 FROM_CPU_INTR0 = 28,
365 #[doc = "29 - FROM_CPU_INTR1"]
366 FROM_CPU_INTR1 = 29,
367 #[doc = "30 - FROM_CPU_INTR2"]
368 FROM_CPU_INTR2 = 30,
369 #[doc = "31 - FROM_CPU_INTR3"]
370 FROM_CPU_INTR3 = 31,
371 #[doc = "32 - SPI1"]
372 SPI1 = 32,
373 #[doc = "33 - SPI2"]
374 SPI2 = 33,
375 #[doc = "34 - SPI3"]
376 SPI3 = 34,
377 #[doc = "35 - I2S0"]
378 I2S0 = 35,
379 #[doc = "36 - I2S1"]
380 I2S1 = 36,
381 #[doc = "37 - UART0"]
382 UART0 = 37,
383 #[doc = "38 - UART1"]
384 UART1 = 38,
385 #[doc = "39 - UART2"]
386 UART2 = 39,
387 #[doc = "40 - SDIO_HOST"]
388 SDIO_HOST = 40,
389 #[doc = "45 - LEDC"]
390 LEDC = 45,
391 #[doc = "46 - EFUSE"]
392 EFUSE = 46,
393 #[doc = "47 - TWAI0"]
394 TWAI0 = 47,
395 #[doc = "48 - USB"]
396 USB = 48,
397 #[doc = "49 - RTC_CORE"]
398 RTC_CORE = 49,
399 #[doc = "50 - RMT"]
400 RMT = 50,
401 #[doc = "51 - PCNT"]
402 PCNT = 51,
403 #[doc = "52 - I2C_EXT0"]
404 I2C_EXT0 = 52,
405 #[doc = "53 - I2C_EXT1"]
406 I2C_EXT1 = 53,
407 #[doc = "54 - RSA"]
408 RSA = 54,
409 #[doc = "55 - SHA"]
410 SHA = 55,
411 #[doc = "56 - AES"]
412 AES = 56,
413 #[doc = "57 - SPI2_DMA"]
414 SPI2_DMA = 57,
415 #[doc = "58 - SPI3_DMA"]
416 SPI3_DMA = 58,
417 #[doc = "59 - WDT"]
418 WDT = 59,
419 #[doc = "60 - TIMER1"]
420 TIMER1 = 60,
421 #[doc = "61 - TIMER2"]
422 TIMER2 = 61,
423 #[doc = "62 - TG0_T0_EDGE"]
424 TG0_T0_EDGE = 62,
425 #[doc = "63 - TG0_T1_EDGE"]
426 TG0_T1_EDGE = 63,
427 #[doc = "64 - TG0_WDT_EDGE"]
428 TG0_WDT_EDGE = 64,
429 #[doc = "65 - TG0_LACT_EDGE"]
430 TG0_LACT_EDGE = 65,
431 #[doc = "66 - TG1_T0_EDGE"]
432 TG1_T0_EDGE = 66,
433 #[doc = "67 - TG1_T1_EDGE"]
434 TG1_T1_EDGE = 67,
435 #[doc = "68 - TG1_WDT_EDGE"]
436 TG1_WDT_EDGE = 68,
437 #[doc = "69 - TG1_LACT_EDGE"]
438 TG1_LACT_EDGE = 69,
439 #[doc = "70 - CACHE_IA"]
440 CACHE_IA = 70,
441 #[doc = "71 - SYSTIMER_TARGET0"]
442 SYSTIMER_TARGET0 = 71,
443 #[doc = "72 - SYSTIMER_TARGET1"]
444 SYSTIMER_TARGET1 = 72,
445 #[doc = "73 - SYSTIMER_TARGET2"]
446 SYSTIMER_TARGET2 = 73,
447 #[doc = "75 - PMS_PRO_IRAM0_ILG"]
448 PMS_PRO_IRAM0_ILG = 75,
449 #[doc = "76 - PMS_PRO_DRAM0_ILG"]
450 PMS_PRO_DRAM0_ILG = 76,
451 #[doc = "77 - PMS_PRO_DPORT_ILG"]
452 PMS_PRO_DPORT_ILG = 77,
453 #[doc = "78 - PMS_PRO_AHB_ILG"]
454 PMS_PRO_AHB_ILG = 78,
455 #[doc = "79 - PMS_PRO_CACHE_ILG"]
456 PMS_PRO_CACHE_ILG = 79,
457 #[doc = "80 - PMS_DMA_APB_I_ILG"]
458 PMS_DMA_APB_I_ILG = 80,
459 #[doc = "81 - PMS_DMA_RX_I_ILG"]
460 PMS_DMA_RX_I_ILG = 81,
461 #[doc = "82 - PMS_DMA_TX_I_ILG"]
462 PMS_DMA_TX_I_ILG = 82,
463 #[doc = "83 - SPI0_REJECT_CACHE"]
464 SPI0_REJECT_CACHE = 83,
465 #[doc = "84 - DMA_COPY"]
466 DMA_COPY = 84,
467 #[doc = "85 - SPI4_DMA"]
468 SPI4_DMA = 85,
469 #[doc = "86 - SPI4"]
470 SPI4 = 86,
471 #[doc = "87 - ICACHE_PRELOAD"]
472 ICACHE_PRELOAD = 87,
473 #[doc = "88 - DCACHE_PRELOAD"]
474 DCACHE_PRELOAD = 88,
475 #[doc = "89 - APB_ADC"]
476 APB_ADC = 89,
477 #[doc = "90 - CRYPTO_DMA"]
478 CRYPTO_DMA = 90,
479 #[doc = "91 - CPU_PERI_ERR"]
480 CPU_PERI_ERR = 91,
481 #[doc = "92 - APB_PERI_ERR"]
482 APB_PERI_ERR = 92,
483 #[doc = "93 - DCACHE_SYNC"]
484 DCACHE_SYNC = 93,
485 #[doc = "94 - ICACHE_SYNC"]
486 ICACHE_SYNC = 94,
487}
488#[doc = r" TryFromInterruptError"]
489#[cfg_attr(feature = "defmt", derive(defmt::Format))]
490#[derive(Debug, Copy, Clone)]
491pub struct TryFromInterruptError(());
492impl Interrupt {
493 #[doc = r" Attempt to convert a given value into an `Interrupt`"]
494 #[inline]
495 pub fn try_from(value: u16) -> Result<Self, TryFromInterruptError> {
496 match value {
497 0 => Ok(Interrupt::WIFI_MAC),
498 1 => Ok(Interrupt::WIFI_NMI),
499 2 => Ok(Interrupt::WIFI_PWR),
500 3 => Ok(Interrupt::WIFI_BB),
501 4 => Ok(Interrupt::BT_MAC),
502 5 => Ok(Interrupt::BT_BB),
503 6 => Ok(Interrupt::BT_BB_NMI),
504 7 => Ok(Interrupt::RWBT),
505 8 => Ok(Interrupt::RWBLE),
506 9 => Ok(Interrupt::RWBT_NMI),
507 10 => Ok(Interrupt::RWBLE_NMI),
508 11 => Ok(Interrupt::SLC0),
509 12 => Ok(Interrupt::SLC1),
510 13 => Ok(Interrupt::UHCI0),
511 14 => Ok(Interrupt::UHCI1),
512 15 => Ok(Interrupt::TG0_T0_LEVEL),
513 16 => Ok(Interrupt::TG0_T1_LEVEL),
514 17 => Ok(Interrupt::TG0_WDT_LEVEL),
515 18 => Ok(Interrupt::TG0_LACT_LEVEL),
516 19 => Ok(Interrupt::TG1_T0_LEVEL),
517 20 => Ok(Interrupt::TG1_T1_LEVEL),
518 21 => Ok(Interrupt::TG1_WDT_LEVEL),
519 22 => Ok(Interrupt::TG1_LACT_LEVEL),
520 23 => Ok(Interrupt::GPIO),
521 24 => Ok(Interrupt::GPIO_NMI),
522 25 => Ok(Interrupt::GPIO_INTR_2),
523 26 => Ok(Interrupt::GPIO_NMI_2),
524 27 => Ok(Interrupt::DEDICATED_GPIO),
525 28 => Ok(Interrupt::FROM_CPU_INTR0),
526 29 => Ok(Interrupt::FROM_CPU_INTR1),
527 30 => Ok(Interrupt::FROM_CPU_INTR2),
528 31 => Ok(Interrupt::FROM_CPU_INTR3),
529 32 => Ok(Interrupt::SPI1),
530 33 => Ok(Interrupt::SPI2),
531 34 => Ok(Interrupt::SPI3),
532 35 => Ok(Interrupt::I2S0),
533 36 => Ok(Interrupt::I2S1),
534 37 => Ok(Interrupt::UART0),
535 38 => Ok(Interrupt::UART1),
536 39 => Ok(Interrupt::UART2),
537 40 => Ok(Interrupt::SDIO_HOST),
538 45 => Ok(Interrupt::LEDC),
539 46 => Ok(Interrupt::EFUSE),
540 47 => Ok(Interrupt::TWAI0),
541 48 => Ok(Interrupt::USB),
542 49 => Ok(Interrupt::RTC_CORE),
543 50 => Ok(Interrupt::RMT),
544 51 => Ok(Interrupt::PCNT),
545 52 => Ok(Interrupt::I2C_EXT0),
546 53 => Ok(Interrupt::I2C_EXT1),
547 54 => Ok(Interrupt::RSA),
548 55 => Ok(Interrupt::SHA),
549 56 => Ok(Interrupt::AES),
550 57 => Ok(Interrupt::SPI2_DMA),
551 58 => Ok(Interrupt::SPI3_DMA),
552 59 => Ok(Interrupt::WDT),
553 60 => Ok(Interrupt::TIMER1),
554 61 => Ok(Interrupt::TIMER2),
555 62 => Ok(Interrupt::TG0_T0_EDGE),
556 63 => Ok(Interrupt::TG0_T1_EDGE),
557 64 => Ok(Interrupt::TG0_WDT_EDGE),
558 65 => Ok(Interrupt::TG0_LACT_EDGE),
559 66 => Ok(Interrupt::TG1_T0_EDGE),
560 67 => Ok(Interrupt::TG1_T1_EDGE),
561 68 => Ok(Interrupt::TG1_WDT_EDGE),
562 69 => Ok(Interrupt::TG1_LACT_EDGE),
563 70 => Ok(Interrupt::CACHE_IA),
564 71 => Ok(Interrupt::SYSTIMER_TARGET0),
565 72 => Ok(Interrupt::SYSTIMER_TARGET1),
566 73 => Ok(Interrupt::SYSTIMER_TARGET2),
567 75 => Ok(Interrupt::PMS_PRO_IRAM0_ILG),
568 76 => Ok(Interrupt::PMS_PRO_DRAM0_ILG),
569 77 => Ok(Interrupt::PMS_PRO_DPORT_ILG),
570 78 => Ok(Interrupt::PMS_PRO_AHB_ILG),
571 79 => Ok(Interrupt::PMS_PRO_CACHE_ILG),
572 80 => Ok(Interrupt::PMS_DMA_APB_I_ILG),
573 81 => Ok(Interrupt::PMS_DMA_RX_I_ILG),
574 82 => Ok(Interrupt::PMS_DMA_TX_I_ILG),
575 83 => Ok(Interrupt::SPI0_REJECT_CACHE),
576 84 => Ok(Interrupt::DMA_COPY),
577 85 => Ok(Interrupt::SPI4_DMA),
578 86 => Ok(Interrupt::SPI4),
579 87 => Ok(Interrupt::ICACHE_PRELOAD),
580 88 => Ok(Interrupt::DCACHE_PRELOAD),
581 89 => Ok(Interrupt::APB_ADC),
582 90 => Ok(Interrupt::CRYPTO_DMA),
583 91 => Ok(Interrupt::CPU_PERI_ERR),
584 92 => Ok(Interrupt::APB_PERI_ERR),
585 93 => Ok(Interrupt::DCACHE_SYNC),
586 94 => Ok(Interrupt::ICACHE_SYNC),
587 _ => Err(TryFromInterruptError(())),
588 }
589 }
590}
591#[doc = "AES (Advanced Encryption Standard) Accelerator"]
592pub type AES = crate::Periph<aes::RegisterBlock, 0x6003_a000>;
593impl core::fmt::Debug for AES {
594 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
595 f.debug_struct("AES").finish()
596 }
597}
598#[doc = "AES (Advanced Encryption Standard) Accelerator"]
599pub mod aes;
600#[doc = "SAR (Successive Approximation Register) Analog-to-Digital Converter"]
601pub type APB_SARADC = crate::Periph<apb_saradc::RegisterBlock, 0x3f44_0000>;
602impl core::fmt::Debug for APB_SARADC {
603 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
604 f.debug_struct("APB_SARADC").finish()
605 }
606}
607#[doc = "SAR (Successive Approximation Register) Analog-to-Digital Converter"]
608pub mod apb_saradc;
609#[doc = "BB Peripheral"]
610pub type BB = crate::Periph<bb::RegisterBlock, 0x3f41_d000>;
611impl core::fmt::Debug for BB {
612 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
613 f.debug_struct("BB").finish()
614 }
615}
616#[doc = "BB Peripheral"]
617pub mod bb;
618#[doc = "DEDICATED_GPIO Peripheral"]
619pub type DEDICATED_GPIO = crate::Periph<dedicated_gpio::RegisterBlock, 0x3f4c_f000>;
620impl core::fmt::Debug for DEDICATED_GPIO {
621 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
622 f.debug_struct("DEDICATED_GPIO").finish()
623 }
624}
625#[doc = "DEDICATED_GPIO Peripheral"]
626pub mod dedicated_gpio;
627#[doc = "I2C Analog Master"]
628pub type I2C_ANA_MST = crate::Periph<i2c_ana_mst::RegisterBlock, 0x6000_e000>;
629impl core::fmt::Debug for I2C_ANA_MST {
630 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
631 f.debug_struct("I2C_ANA_MST").finish()
632 }
633}
634#[doc = "I2C Analog Master"]
635pub mod i2c_ana_mst;
636#[doc = "MAC controller for Wi-Fi peripheral"]
637pub type WIFI = crate::Periph<wifi::RegisterBlock, 0x6003_3000>;
638impl core::fmt::Debug for WIFI {
639 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
640 f.debug_struct("WIFI").finish()
641 }
642}
643#[doc = "MAC controller for Wi-Fi peripheral"]
644pub mod wifi;
645#[doc = "Digital Signature"]
646pub type DS = crate::Periph<ds::RegisterBlock, 0x6003_d000>;
647impl core::fmt::Debug for DS {
648 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
649 f.debug_struct("DS").finish()
650 }
651}
652#[doc = "Digital Signature"]
653pub mod ds;
654#[doc = "eFuse Controller"]
655pub type EFUSE = crate::Periph<efuse::RegisterBlock, 0x3f41_a000>;
656impl core::fmt::Debug for EFUSE {
657 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
658 f.debug_struct("EFUSE").finish()
659 }
660}
661#[doc = "eFuse Controller"]
662pub mod efuse;
663#[doc = "NRX Peripheral"]
664pub type NRX = crate::Periph<nrx::RegisterBlock, 0x3f41_cc00>;
665impl core::fmt::Debug for NRX {
666 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
667 f.debug_struct("NRX").finish()
668 }
669}
670#[doc = "NRX Peripheral"]
671pub mod nrx;
672#[doc = "External Memory"]
673pub type EXTMEM = crate::Periph<extmem::RegisterBlock, 0x6180_0000>;
674impl core::fmt::Debug for EXTMEM {
675 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
676 f.debug_struct("EXTMEM").finish()
677 }
678}
679#[doc = "External Memory"]
680pub mod extmem;
681#[doc = "General Purpose Input/Output"]
682pub type GPIO = crate::Periph<gpio::RegisterBlock, 0x3f40_4000>;
683impl core::fmt::Debug for GPIO {
684 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
685 f.debug_struct("GPIO").finish()
686 }
687}
688#[doc = "General Purpose Input/Output"]
689pub mod gpio;
690#[doc = "Sigma-Delta Modulation"]
691pub type GPIO_SD = crate::Periph<gpio_sd::RegisterBlock, 0x3f40_4f00>;
692impl core::fmt::Debug for GPIO_SD {
693 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
694 f.debug_struct("GPIO_SD").finish()
695 }
696}
697#[doc = "Sigma-Delta Modulation"]
698pub mod gpio_sd;
699#[doc = "FE2 Peripheral"]
700pub type FE2 = crate::Periph<fe2::RegisterBlock, 0x3f40_5000>;
701impl core::fmt::Debug for FE2 {
702 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
703 f.debug_struct("FE2").finish()
704 }
705}
706#[doc = "FE2 Peripheral"]
707pub mod fe2;
708#[doc = "FE Peripheral"]
709pub type FE = crate::Periph<fe::RegisterBlock, 0x3f40_6000>;
710impl core::fmt::Debug for FE {
711 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
712 f.debug_struct("FE").finish()
713 }
714}
715#[doc = "FE Peripheral"]
716pub mod fe;
717#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"]
718pub type HMAC = crate::Periph<hmac::RegisterBlock, 0x6003_e000>;
719impl core::fmt::Debug for HMAC {
720 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
721 f.debug_struct("HMAC").finish()
722 }
723}
724#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"]
725pub mod hmac;
726#[doc = "Crypto DMA Controller"]
727pub type CRYPTO_DMA = crate::Periph<crypto_dma::RegisterBlock, 0x6003_f000>;
728impl core::fmt::Debug for CRYPTO_DMA {
729 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
730 f.debug_struct("CRYPTO_DMA").finish()
731 }
732}
733#[doc = "Crypto DMA Controller"]
734pub mod crypto_dma;
735#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
736pub type I2C0 = crate::Periph<i2c0::RegisterBlock, 0x3f41_3000>;
737impl core::fmt::Debug for I2C0 {
738 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
739 f.debug_struct("I2C0").finish()
740 }
741}
742#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
743pub mod i2c0;
744#[doc = "I2C (Inter-Integrated Circuit) Controller 1"]
745pub type I2C1 = crate::Periph<i2c0::RegisterBlock, 0x3f42_7000>;
746impl core::fmt::Debug for I2C1 {
747 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
748 f.debug_struct("I2C1").finish()
749 }
750}
751#[doc = "I2C (Inter-Integrated Circuit) Controller 1"]
752pub use self::i2c0 as i2c1;
753#[doc = "I2S (Inter-IC Sound) Controller 0"]
754pub type I2S0 = crate::Periph<i2s0::RegisterBlock, 0x3f40_f000>;
755impl core::fmt::Debug for I2S0 {
756 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
757 f.debug_struct("I2S0").finish()
758 }
759}
760#[doc = "I2S (Inter-IC Sound) Controller 0"]
761pub mod i2s0;
762#[doc = "Interrupt Controller (Core 0)"]
763pub type INTERRUPT_CORE0 = crate::Periph<interrupt_core0::RegisterBlock, 0x3f4c_2000>;
764impl core::fmt::Debug for INTERRUPT_CORE0 {
765 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
766 f.debug_struct("INTERRUPT_CORE0").finish()
767 }
768}
769#[doc = "Interrupt Controller (Core 0)"]
770pub mod interrupt_core0;
771#[doc = "Copy DMA Controller"]
772pub type COPY_DMA = crate::Periph<copy_dma::RegisterBlock, 0x3f4c_3000>;
773impl core::fmt::Debug for COPY_DMA {
774 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
775 f.debug_struct("COPY_DMA").finish()
776 }
777}
778#[doc = "Copy DMA Controller"]
779pub mod copy_dma;
780#[doc = "Input/Output Multiplexer"]
781pub type IO_MUX = crate::Periph<io_mux::RegisterBlock, 0x3f40_9000>;
782impl core::fmt::Debug for IO_MUX {
783 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
784 f.debug_struct("IO_MUX").finish()
785 }
786}
787#[doc = "Input/Output Multiplexer"]
788pub mod io_mux;
789#[doc = "LED Control PWM (Pulse Width Modulation)"]
790pub type LEDC = crate::Periph<ledc::RegisterBlock, 0x3f41_9000>;
791impl core::fmt::Debug for LEDC {
792 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
793 f.debug_struct("LEDC").finish()
794 }
795}
796#[doc = "LED Control PWM (Pulse Width Modulation)"]
797pub mod ledc;
798#[doc = "Pulse Count Controller"]
799pub type PCNT = crate::Periph<pcnt::RegisterBlock, 0x3f41_7000>;
800impl core::fmt::Debug for PCNT {
801 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
802 f.debug_struct("PCNT").finish()
803 }
804}
805#[doc = "Pulse Count Controller"]
806pub mod pcnt;
807#[doc = "Permissions Controller"]
808pub type PMS = crate::Periph<pms::RegisterBlock, 0x3f4c_1000>;
809impl core::fmt::Debug for PMS {
810 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
811 f.debug_struct("PMS").finish()
812 }
813}
814#[doc = "Permissions Controller"]
815pub mod pms;
816#[doc = "Remote Control"]
817pub type RMT = crate::Periph<rmt::RegisterBlock, 0x3f41_6000>;
818impl core::fmt::Debug for RMT {
819 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
820 f.debug_struct("RMT").finish()
821 }
822}
823#[doc = "Remote Control"]
824pub mod rmt;
825#[doc = "Hardware Random Number Generator"]
826pub type RNG = crate::Periph<rng::RegisterBlock, 0x6003_5000>;
827impl core::fmt::Debug for RNG {
828 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
829 f.debug_struct("RNG").finish()
830 }
831}
832#[doc = "Hardware Random Number Generator"]
833pub mod rng;
834#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
835pub type RSA = crate::Periph<rsa::RegisterBlock, 0x6003_c000>;
836impl core::fmt::Debug for RSA {
837 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
838 f.debug_struct("RSA").finish()
839 }
840}
841#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
842pub mod rsa;
843#[doc = "Low-power Input/Output"]
844pub type RTC_IO = crate::Periph<rtc_io::RegisterBlock, 0x3f40_8400>;
845impl core::fmt::Debug for RTC_IO {
846 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
847 f.debug_struct("RTC_IO").finish()
848 }
849}
850#[doc = "Low-power Input/Output"]
851pub mod rtc_io;
852#[doc = "Real-Time Clock Control"]
853pub type RTC_CNTL = crate::Periph<rtc_cntl::RegisterBlock, 0x3f40_8000>;
854impl core::fmt::Debug for RTC_CNTL {
855 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
856 f.debug_struct("RTC_CNTL").finish()
857 }
858}
859#[doc = "Real-Time Clock Control"]
860pub mod rtc_cntl;
861#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller"]
862pub type RTC_I2C = crate::Periph<rtc_i2c::RegisterBlock, 0x3f40_8c00>;
863impl core::fmt::Debug for RTC_I2C {
864 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
865 f.debug_struct("RTC_I2C").finish()
866 }
867}
868#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller"]
869pub mod rtc_i2c;
870#[doc = "SENS Peripheral"]
871pub type SENS = crate::Periph<sens::RegisterBlock, 0x3f40_8800>;
872impl core::fmt::Debug for SENS {
873 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
874 f.debug_struct("SENS").finish()
875 }
876}
877#[doc = "SENS Peripheral"]
878pub mod sens;
879#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
880pub type SHA = crate::Periph<sha::RegisterBlock, 0x6003_b000>;
881impl core::fmt::Debug for SHA {
882 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
883 f.debug_struct("SHA").finish()
884 }
885}
886#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
887pub mod sha;
888#[doc = "SPI (Serial Peripheral Interface) Controller 2 (GPSPI)"]
889pub type SPI2 = crate::Periph<spi2::RegisterBlock, 0x3f42_4000>;
890impl core::fmt::Debug for SPI2 {
891 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
892 f.debug_struct("SPI2").finish()
893 }
894}
895#[doc = "SPI (Serial Peripheral Interface) Controller 2 (GPSPI)"]
896pub mod spi2;
897#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
898pub type SPI1 = crate::Periph<spi0::RegisterBlock, 0x3f40_2000>;
899impl core::fmt::Debug for SPI1 {
900 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
901 f.debug_struct("SPI1").finish()
902 }
903}
904#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
905pub use self::spi0 as spi1;
906#[doc = "SPI (Serial Peripheral Interface) Controller 0 (MEMSPI)"]
907pub type SPI0 = crate::Periph<spi0::RegisterBlock, 0x3f40_3000>;
908impl core::fmt::Debug for SPI0 {
909 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
910 f.debug_struct("SPI0").finish()
911 }
912}
913#[doc = "SPI (Serial Peripheral Interface) Controller 0 (MEMSPI)"]
914pub mod spi0;
915#[doc = "SPI (Serial Peripheral Interface) Controller 3"]
916pub type SPI3 = crate::Periph<spi2::RegisterBlock, 0x3f42_5000>;
917impl core::fmt::Debug for SPI3 {
918 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
919 f.debug_struct("SPI3").finish()
920 }
921}
922#[doc = "SPI (Serial Peripheral Interface) Controller 3"]
923pub use self::spi2 as spi3;
924#[doc = "SPI (Serial Peripheral Interface) Controller 4"]
925pub type SPI4 = crate::Periph<spi2::RegisterBlock, 0x3f43_7000>;
926impl core::fmt::Debug for SPI4 {
927 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
928 f.debug_struct("SPI4").finish()
929 }
930}
931#[doc = "SPI (Serial Peripheral Interface) Controller 4"]
932pub use self::spi2 as spi4;
933#[doc = "SYSCON Peripheral"]
934pub type SYSCON = crate::Periph<syscon::RegisterBlock, 0x3f42_6000>;
935impl core::fmt::Debug for SYSCON {
936 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
937 f.debug_struct("SYSCON").finish()
938 }
939}
940#[doc = "SYSCON Peripheral"]
941pub mod syscon;
942#[doc = "System Configuration Registers"]
943pub type SYSTEM = crate::Periph<system::RegisterBlock, 0x3f4c_0000>;
944impl core::fmt::Debug for SYSTEM {
945 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
946 f.debug_struct("SYSTEM").finish()
947 }
948}
949#[doc = "System Configuration Registers"]
950pub mod system;
951#[doc = "System Timer"]
952pub type SYSTIMER = crate::Periph<systimer::RegisterBlock, 0x3f42_3000>;
953impl core::fmt::Debug for SYSTIMER {
954 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
955 f.debug_struct("SYSTIMER").finish()
956 }
957}
958#[doc = "System Timer"]
959pub mod systimer;
960#[doc = "Timer Group 0"]
961pub type TIMG0 = crate::Periph<timg0::RegisterBlock, 0x3f41_f000>;
962impl core::fmt::Debug for TIMG0 {
963 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
964 f.debug_struct("TIMG0").finish()
965 }
966}
967#[doc = "Timer Group 0"]
968pub mod timg0;
969#[doc = "Timer Group 1"]
970pub type TIMG1 = crate::Periph<timg0::RegisterBlock, 0x3f42_0000>;
971impl core::fmt::Debug for TIMG1 {
972 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
973 f.debug_struct("TIMG1").finish()
974 }
975}
976#[doc = "Timer Group 1"]
977pub use self::timg0 as timg1;
978#[doc = "Two-Wire Automotive Interface"]
979pub type TWAI0 = crate::Periph<twai0::RegisterBlock, 0x3f42_b000>;
980impl core::fmt::Debug for TWAI0 {
981 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
982 f.debug_struct("TWAI0").finish()
983 }
984}
985#[doc = "Two-Wire Automotive Interface"]
986pub mod twai0;
987#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
988pub type UART0 = crate::Periph<uart0::RegisterBlock, 0x3f40_0000>;
989impl core::fmt::Debug for UART0 {
990 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
991 f.debug_struct("UART0").finish()
992 }
993}
994#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
995pub mod uart0;
996#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
997pub type UART1 = crate::Periph<uart0::RegisterBlock, 0x3f41_0000>;
998impl core::fmt::Debug for UART1 {
999 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1000 f.debug_struct("UART1").finish()
1001 }
1002}
1003#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
1004pub use self::uart0 as uart1;
1005#[doc = "Universal Host Controller Interface 0"]
1006pub type UHCI0 = crate::Periph<uhci0::RegisterBlock, 0x3f41_4000>;
1007impl core::fmt::Debug for UHCI0 {
1008 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1009 f.debug_struct("UHCI0").finish()
1010 }
1011}
1012#[doc = "Universal Host Controller Interface 0"]
1013pub mod uhci0;
1014#[doc = "USB OTG (On-The-Go)"]
1015pub type USB0 = crate::Periph<usb0::RegisterBlock, 0x6008_0000>;
1016impl core::fmt::Debug for USB0 {
1017 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1018 f.debug_struct("USB0").finish()
1019 }
1020}
1021#[doc = "USB OTG (On-The-Go)"]
1022pub mod usb0;
1023#[doc = "USB_WRAP Peripheral"]
1024pub type USB_WRAP = crate::Periph<usb_wrap::RegisterBlock, 0x3f43_9000>;
1025impl core::fmt::Debug for USB_WRAP {
1026 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1027 f.debug_struct("USB_WRAP").finish()
1028 }
1029}
1030#[doc = "USB_WRAP Peripheral"]
1031pub mod usb_wrap;
1032#[doc = "XTS-AES-128 Flash Encryption"]
1033pub type XTS_AES = crate::Periph<xts_aes::RegisterBlock, 0x6003_a100>;
1034impl core::fmt::Debug for XTS_AES {
1035 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1036 f.debug_struct("XTS_AES").finish()
1037 }
1038}
1039#[doc = "XTS-AES-128 Flash Encryption"]
1040pub mod xts_aes;
1041#[no_mangle]
1042static mut DEVICE_PERIPHERALS: bool = false;
1043#[doc = r" All the peripherals."]
1044#[allow(non_snake_case)]
1045pub struct Peripherals {
1046 #[doc = "AES"]
1047 pub AES: AES,
1048 #[doc = "APB_SARADC"]
1049 pub APB_SARADC: APB_SARADC,
1050 #[doc = "BB"]
1051 pub BB: BB,
1052 #[doc = "DEDICATED_GPIO"]
1053 pub DEDICATED_GPIO: DEDICATED_GPIO,
1054 #[doc = "I2C_ANA_MST"]
1055 pub I2C_ANA_MST: I2C_ANA_MST,
1056 #[doc = "WIFI"]
1057 pub WIFI: WIFI,
1058 #[doc = "DS"]
1059 pub DS: DS,
1060 #[doc = "EFUSE"]
1061 pub EFUSE: EFUSE,
1062 #[doc = "NRX"]
1063 pub NRX: NRX,
1064 #[doc = "EXTMEM"]
1065 pub EXTMEM: EXTMEM,
1066 #[doc = "GPIO"]
1067 pub GPIO: GPIO,
1068 #[doc = "GPIO_SD"]
1069 pub GPIO_SD: GPIO_SD,
1070 #[doc = "FE2"]
1071 pub FE2: FE2,
1072 #[doc = "FE"]
1073 pub FE: FE,
1074 #[doc = "HMAC"]
1075 pub HMAC: HMAC,
1076 #[doc = "CRYPTO_DMA"]
1077 pub CRYPTO_DMA: CRYPTO_DMA,
1078 #[doc = "I2C0"]
1079 pub I2C0: I2C0,
1080 #[doc = "I2C1"]
1081 pub I2C1: I2C1,
1082 #[doc = "I2S0"]
1083 pub I2S0: I2S0,
1084 #[doc = "INTERRUPT_CORE0"]
1085 pub INTERRUPT_CORE0: INTERRUPT_CORE0,
1086 #[doc = "COPY_DMA"]
1087 pub COPY_DMA: COPY_DMA,
1088 #[doc = "IO_MUX"]
1089 pub IO_MUX: IO_MUX,
1090 #[doc = "LEDC"]
1091 pub LEDC: LEDC,
1092 #[doc = "PCNT"]
1093 pub PCNT: PCNT,
1094 #[doc = "PMS"]
1095 pub PMS: PMS,
1096 #[doc = "RMT"]
1097 pub RMT: RMT,
1098 #[doc = "RNG"]
1099 pub RNG: RNG,
1100 #[doc = "RSA"]
1101 pub RSA: RSA,
1102 #[doc = "RTC_IO"]
1103 pub RTC_IO: RTC_IO,
1104 #[doc = "RTC_CNTL"]
1105 pub RTC_CNTL: RTC_CNTL,
1106 #[doc = "RTC_I2C"]
1107 pub RTC_I2C: RTC_I2C,
1108 #[doc = "SENS"]
1109 pub SENS: SENS,
1110 #[doc = "SHA"]
1111 pub SHA: SHA,
1112 #[doc = "SPI2"]
1113 pub SPI2: SPI2,
1114 #[doc = "SPI1"]
1115 pub SPI1: SPI1,
1116 #[doc = "SPI0"]
1117 pub SPI0: SPI0,
1118 #[doc = "SPI3"]
1119 pub SPI3: SPI3,
1120 #[doc = "SPI4"]
1121 pub SPI4: SPI4,
1122 #[doc = "SYSCON"]
1123 pub SYSCON: SYSCON,
1124 #[doc = "SYSTEM"]
1125 pub SYSTEM: SYSTEM,
1126 #[doc = "SYSTIMER"]
1127 pub SYSTIMER: SYSTIMER,
1128 #[doc = "TIMG0"]
1129 pub TIMG0: TIMG0,
1130 #[doc = "TIMG1"]
1131 pub TIMG1: TIMG1,
1132 #[doc = "TWAI0"]
1133 pub TWAI0: TWAI0,
1134 #[doc = "UART0"]
1135 pub UART0: UART0,
1136 #[doc = "UART1"]
1137 pub UART1: UART1,
1138 #[doc = "UHCI0"]
1139 pub UHCI0: UHCI0,
1140 #[doc = "USB0"]
1141 pub USB0: USB0,
1142 #[doc = "USB_WRAP"]
1143 pub USB_WRAP: USB_WRAP,
1144 #[doc = "XTS_AES"]
1145 pub XTS_AES: XTS_AES,
1146}
1147impl Peripherals {
1148 #[doc = r" Returns all the peripherals *once*."]
1149 #[cfg(feature = "critical-section")]
1150 #[inline]
1151 pub fn take() -> Option<Self> {
1152 critical_section::with(|_| {
1153 if unsafe { DEVICE_PERIPHERALS } {
1154 return None;
1155 }
1156 Some(unsafe { Peripherals::steal() })
1157 })
1158 }
1159 #[doc = r" Unchecked version of `Peripherals::take`."]
1160 #[doc = r""]
1161 #[doc = r" # Safety"]
1162 #[doc = r""]
1163 #[doc = r" Each of the returned peripherals must be used at most once."]
1164 #[inline]
1165 pub unsafe fn steal() -> Self {
1166 DEVICE_PERIPHERALS = true;
1167 Peripherals {
1168 AES: AES::steal(),
1169 APB_SARADC: APB_SARADC::steal(),
1170 BB: BB::steal(),
1171 DEDICATED_GPIO: DEDICATED_GPIO::steal(),
1172 I2C_ANA_MST: I2C_ANA_MST::steal(),
1173 WIFI: WIFI::steal(),
1174 DS: DS::steal(),
1175 EFUSE: EFUSE::steal(),
1176 NRX: NRX::steal(),
1177 EXTMEM: EXTMEM::steal(),
1178 GPIO: GPIO::steal(),
1179 GPIO_SD: GPIO_SD::steal(),
1180 FE2: FE2::steal(),
1181 FE: FE::steal(),
1182 HMAC: HMAC::steal(),
1183 CRYPTO_DMA: CRYPTO_DMA::steal(),
1184 I2C0: I2C0::steal(),
1185 I2C1: I2C1::steal(),
1186 I2S0: I2S0::steal(),
1187 INTERRUPT_CORE0: INTERRUPT_CORE0::steal(),
1188 COPY_DMA: COPY_DMA::steal(),
1189 IO_MUX: IO_MUX::steal(),
1190 LEDC: LEDC::steal(),
1191 PCNT: PCNT::steal(),
1192 PMS: PMS::steal(),
1193 RMT: RMT::steal(),
1194 RNG: RNG::steal(),
1195 RSA: RSA::steal(),
1196 RTC_IO: RTC_IO::steal(),
1197 RTC_CNTL: RTC_CNTL::steal(),
1198 RTC_I2C: RTC_I2C::steal(),
1199 SENS: SENS::steal(),
1200 SHA: SHA::steal(),
1201 SPI2: SPI2::steal(),
1202 SPI1: SPI1::steal(),
1203 SPI0: SPI0::steal(),
1204 SPI3: SPI3::steal(),
1205 SPI4: SPI4::steal(),
1206 SYSCON: SYSCON::steal(),
1207 SYSTEM: SYSTEM::steal(),
1208 SYSTIMER: SYSTIMER::steal(),
1209 TIMG0: TIMG0::steal(),
1210 TIMG1: TIMG1::steal(),
1211 TWAI0: TWAI0::steal(),
1212 UART0: UART0::steal(),
1213 UART1: UART1::steal(),
1214 UHCI0: UHCI0::steal(),
1215 USB0: USB0::steal(),
1216 USB_WRAP: USB_WRAP::steal(),
1217 XTS_AES: XTS_AES::steal(),
1218 }
1219 }
1220}