esp32s2/io_mux/
pin_ctrl.rs

1#[doc = "Register `PIN_CTRL` reader"]
2pub type R = crate::R<PIN_CTRL_SPEC>;
3#[doc = "Register `PIN_CTRL` writer"]
4pub type W = crate::W<PIN_CTRL_SPEC>;
5#[doc = "Field `PIN_CLK_OUT1` reader - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled."]
6pub type PIN_CLK_OUT1_R = crate::FieldReader;
7#[doc = "Field `PIN_CLK_OUT1` writer - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled."]
8pub type PIN_CLK_OUT1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `PIN_CLK_OUT2` reader - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled."]
10pub type PIN_CLK_OUT2_R = crate::FieldReader;
11#[doc = "Field `PIN_CLK_OUT2` writer - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled."]
12pub type PIN_CLK_OUT2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `PIN_CLK_OUT3` reader - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled."]
14pub type PIN_CLK_OUT3_R = crate::FieldReader;
15#[doc = "Field `PIN_CLK_OUT3` writer - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled."]
16pub type PIN_CLK_OUT3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17#[doc = "Field `SWITCH_PRT_NUM` reader - IO pin power switch delay, delay unit is one APB clock."]
18pub type SWITCH_PRT_NUM_R = crate::FieldReader;
19#[doc = "Field `SWITCH_PRT_NUM` writer - IO pin power switch delay, delay unit is one APB clock."]
20pub type SWITCH_PRT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `PAD_POWER_CTRL` reader - Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V."]
22pub type PAD_POWER_CTRL_R = crate::BitReader;
23#[doc = "Field `PAD_POWER_CTRL` writer - Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V."]
24pub type PAD_POWER_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bits 0:3 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled."]
27    #[inline(always)]
28    pub fn pin_clk_out1(&self) -> PIN_CLK_OUT1_R {
29        PIN_CLK_OUT1_R::new((self.bits & 0x0f) as u8)
30    }
31    #[doc = "Bits 4:7 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled."]
32    #[inline(always)]
33    pub fn pin_clk_out2(&self) -> PIN_CLK_OUT2_R {
34        PIN_CLK_OUT2_R::new(((self.bits >> 4) & 0x0f) as u8)
35    }
36    #[doc = "Bits 8:11 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled."]
37    #[inline(always)]
38    pub fn pin_clk_out3(&self) -> PIN_CLK_OUT3_R {
39        PIN_CLK_OUT3_R::new(((self.bits >> 8) & 0x0f) as u8)
40    }
41    #[doc = "Bits 12:14 - IO pin power switch delay, delay unit is one APB clock."]
42    #[inline(always)]
43    pub fn switch_prt_num(&self) -> SWITCH_PRT_NUM_R {
44        SWITCH_PRT_NUM_R::new(((self.bits >> 12) & 7) as u8)
45    }
46    #[doc = "Bit 15 - Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V."]
47    #[inline(always)]
48    pub fn pad_power_ctrl(&self) -> PAD_POWER_CTRL_R {
49        PAD_POWER_CTRL_R::new(((self.bits >> 15) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("PIN_CTRL")
56            .field("pin_clk_out1", &self.pin_clk_out1())
57            .field("pin_clk_out2", &self.pin_clk_out2())
58            .field("pin_clk_out3", &self.pin_clk_out3())
59            .field("switch_prt_num", &self.switch_prt_num())
60            .field("pad_power_ctrl", &self.pad_power_ctrl())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bits 0:3 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled."]
66    #[inline(always)]
67    pub fn pin_clk_out1(&mut self) -> PIN_CLK_OUT1_W<PIN_CTRL_SPEC> {
68        PIN_CLK_OUT1_W::new(self, 0)
69    }
70    #[doc = "Bits 4:7 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled."]
71    #[inline(always)]
72    pub fn pin_clk_out2(&mut self) -> PIN_CLK_OUT2_W<PIN_CTRL_SPEC> {
73        PIN_CLK_OUT2_W::new(self, 4)
74    }
75    #[doc = "Bits 8:11 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled."]
76    #[inline(always)]
77    pub fn pin_clk_out3(&mut self) -> PIN_CLK_OUT3_W<PIN_CTRL_SPEC> {
78        PIN_CLK_OUT3_W::new(self, 8)
79    }
80    #[doc = "Bits 12:14 - IO pin power switch delay, delay unit is one APB clock."]
81    #[inline(always)]
82    pub fn switch_prt_num(&mut self) -> SWITCH_PRT_NUM_W<PIN_CTRL_SPEC> {
83        SWITCH_PRT_NUM_W::new(self, 12)
84    }
85    #[doc = "Bit 15 - Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V."]
86    #[inline(always)]
87    pub fn pad_power_ctrl(&mut self) -> PAD_POWER_CTRL_W<PIN_CTRL_SPEC> {
88        PAD_POWER_CTRL_W::new(self, 15)
89    }
90}
91#[doc = "Clock output configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pin_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct PIN_CTRL_SPEC;
93impl crate::RegisterSpec for PIN_CTRL_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`pin_ctrl::R`](R) reader structure"]
97impl crate::Readable for PIN_CTRL_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`pin_ctrl::W`](W) writer structure"]
99impl crate::Writable for PIN_CTRL_SPEC {
100    type Safety = crate::Unsafe;
101}
102#[doc = "`reset()` method sets PIN_CTRL to value 0x27ff"]
103impl crate::Resettable for PIN_CTRL_SPEC {
104    const RESET_VALUE: u32 = 0x27ff;
105}
esp32s2/io_mux/pin_ctrl.rs

esp32s2/io_mux/
pin_ctrl.rs
