esp32s2/i2s0/
fifo_conf.rs

1#[doc = "Register `FIFO_CONF` reader"]
2pub type R = crate::R<FIFO_CONF_SPEC>;
3#[doc = "Register `FIFO_CONF` writer"]
4pub type W = crate::W<FIFO_CONF_SPEC>;
5#[doc = "Field `RX_DATA_NUM` reader - I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM\\[5:0\\]. (RX FIFO is almost full threshold.)"]
6pub type RX_DATA_NUM_R = crate::FieldReader;
7#[doc = "Field `RX_DATA_NUM` writer - I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM\\[5:0\\]. (RX FIFO is almost full threshold.)"]
8pub type RX_DATA_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `TX_DATA_NUM` reader - I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM\\[5:0\\]. (TX FIFO is almost empty threshold.)"]
10pub type TX_DATA_NUM_R = crate::FieldReader;
11#[doc = "Field `TX_DATA_NUM` writer - I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM\\[5:0\\]. (TX FIFO is almost empty threshold.)"]
12pub type TX_DATA_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `DSCR_EN` reader - Set this bit to enable I2S DMA mode."]
14pub type DSCR_EN_R = crate::BitReader;
15#[doc = "Field `DSCR_EN` writer - Set this bit to enable I2S DMA mode."]
16pub type DSCR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TX_FIFO_MOD` reader - Transmitter FIFO mode configuration bits"]
18pub type TX_FIFO_MOD_R = crate::FieldReader;
19#[doc = "Field `TX_FIFO_MOD` writer - Transmitter FIFO mode configuration bits"]
20pub type TX_FIFO_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `RX_FIFO_MOD` reader - Receiver FIFO mode configuration bits"]
22pub type RX_FIFO_MOD_R = crate::FieldReader;
23#[doc = "Field `RX_FIFO_MOD` writer - Receiver FIFO mode configuration bits"]
24pub type RX_FIFO_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25#[doc = "Field `TX_FIFO_MOD_FORCE_EN` reader - The bit should always be set to 1"]
26pub type TX_FIFO_MOD_FORCE_EN_R = crate::BitReader;
27#[doc = "Field `TX_FIFO_MOD_FORCE_EN` writer - The bit should always be set to 1"]
28pub type TX_FIFO_MOD_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RX_FIFO_MOD_FORCE_EN` reader - The bit should always be set to 1"]
30pub type RX_FIFO_MOD_FORCE_EN_R = crate::BitReader;
31#[doc = "Field `RX_FIFO_MOD_FORCE_EN` writer - The bit should always be set to 1"]
32pub type RX_FIFO_MOD_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RX_FIFO_SYNC` reader - force write back rx data to memory"]
34pub type RX_FIFO_SYNC_R = crate::BitReader;
35#[doc = "Field `RX_FIFO_SYNC` writer - force write back rx data to memory"]
36pub type RX_FIFO_SYNC_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RX_24MSB_EN` reader - Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
38pub type RX_24MSB_EN_R = crate::BitReader;
39#[doc = "Field `RX_24MSB_EN` writer - Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
40pub type RX_24MSB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `TX_24MSB_EN` reader - Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
42pub type TX_24MSB_EN_R = crate::BitReader;
43#[doc = "Field `TX_24MSB_EN` writer - Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
44pub type TX_24MSB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    #[doc = "Bits 0:5 - I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM\\[5:0\\]. (RX FIFO is almost full threshold.)"]
47    #[inline(always)]
48    pub fn rx_data_num(&self) -> RX_DATA_NUM_R {
49        RX_DATA_NUM_R::new((self.bits & 0x3f) as u8)
50    }
51    #[doc = "Bits 6:11 - I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM\\[5:0\\]. (TX FIFO is almost empty threshold.)"]
52    #[inline(always)]
53    pub fn tx_data_num(&self) -> TX_DATA_NUM_R {
54        TX_DATA_NUM_R::new(((self.bits >> 6) & 0x3f) as u8)
55    }
56    #[doc = "Bit 12 - Set this bit to enable I2S DMA mode."]
57    #[inline(always)]
58    pub fn dscr_en(&self) -> DSCR_EN_R {
59        DSCR_EN_R::new(((self.bits >> 12) & 1) != 0)
60    }
61    #[doc = "Bits 13:15 - Transmitter FIFO mode configuration bits"]
62    #[inline(always)]
63    pub fn tx_fifo_mod(&self) -> TX_FIFO_MOD_R {
64        TX_FIFO_MOD_R::new(((self.bits >> 13) & 7) as u8)
65    }
66    #[doc = "Bits 16:18 - Receiver FIFO mode configuration bits"]
67    #[inline(always)]
68    pub fn rx_fifo_mod(&self) -> RX_FIFO_MOD_R {
69        RX_FIFO_MOD_R::new(((self.bits >> 16) & 7) as u8)
70    }
71    #[doc = "Bit 19 - The bit should always be set to 1"]
72    #[inline(always)]
73    pub fn tx_fifo_mod_force_en(&self) -> TX_FIFO_MOD_FORCE_EN_R {
74        TX_FIFO_MOD_FORCE_EN_R::new(((self.bits >> 19) & 1) != 0)
75    }
76    #[doc = "Bit 20 - The bit should always be set to 1"]
77    #[inline(always)]
78    pub fn rx_fifo_mod_force_en(&self) -> RX_FIFO_MOD_FORCE_EN_R {
79        RX_FIFO_MOD_FORCE_EN_R::new(((self.bits >> 20) & 1) != 0)
80    }
81    #[doc = "Bit 21 - force write back rx data to memory"]
82    #[inline(always)]
83    pub fn rx_fifo_sync(&self) -> RX_FIFO_SYNC_R {
84        RX_FIFO_SYNC_R::new(((self.bits >> 21) & 1) != 0)
85    }
86    #[doc = "Bit 22 - Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
87    #[inline(always)]
88    pub fn rx_24msb_en(&self) -> RX_24MSB_EN_R {
89        RX_24MSB_EN_R::new(((self.bits >> 22) & 1) != 0)
90    }
91    #[doc = "Bit 23 - Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
92    #[inline(always)]
93    pub fn tx_24msb_en(&self) -> TX_24MSB_EN_R {
94        TX_24MSB_EN_R::new(((self.bits >> 23) & 1) != 0)
95    }
96}
97#[cfg(feature = "impl-register-debug")]
98impl core::fmt::Debug for R {
99    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100        f.debug_struct("FIFO_CONF")
101            .field("rx_data_num", &self.rx_data_num())
102            .field("tx_data_num", &self.tx_data_num())
103            .field("dscr_en", &self.dscr_en())
104            .field("tx_fifo_mod", &self.tx_fifo_mod())
105            .field("rx_fifo_mod", &self.rx_fifo_mod())
106            .field("tx_fifo_mod_force_en", &self.tx_fifo_mod_force_en())
107            .field("rx_fifo_mod_force_en", &self.rx_fifo_mod_force_en())
108            .field("rx_fifo_sync", &self.rx_fifo_sync())
109            .field("rx_24msb_en", &self.rx_24msb_en())
110            .field("tx_24msb_en", &self.tx_24msb_en())
111            .finish()
112    }
113}
114impl W {
115    #[doc = "Bits 0:5 - I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM\\[5:0\\]. (RX FIFO is almost full threshold.)"]
116    #[inline(always)]
117    pub fn rx_data_num(&mut self) -> RX_DATA_NUM_W<FIFO_CONF_SPEC> {
118        RX_DATA_NUM_W::new(self, 0)
119    }
120    #[doc = "Bits 6:11 - I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM\\[5:0\\]. (TX FIFO is almost empty threshold.)"]
121    #[inline(always)]
122    pub fn tx_data_num(&mut self) -> TX_DATA_NUM_W<FIFO_CONF_SPEC> {
123        TX_DATA_NUM_W::new(self, 6)
124    }
125    #[doc = "Bit 12 - Set this bit to enable I2S DMA mode."]
126    #[inline(always)]
127    pub fn dscr_en(&mut self) -> DSCR_EN_W<FIFO_CONF_SPEC> {
128        DSCR_EN_W::new(self, 12)
129    }
130    #[doc = "Bits 13:15 - Transmitter FIFO mode configuration bits"]
131    #[inline(always)]
132    pub fn tx_fifo_mod(&mut self) -> TX_FIFO_MOD_W<FIFO_CONF_SPEC> {
133        TX_FIFO_MOD_W::new(self, 13)
134    }
135    #[doc = "Bits 16:18 - Receiver FIFO mode configuration bits"]
136    #[inline(always)]
137    pub fn rx_fifo_mod(&mut self) -> RX_FIFO_MOD_W<FIFO_CONF_SPEC> {
138        RX_FIFO_MOD_W::new(self, 16)
139    }
140    #[doc = "Bit 19 - The bit should always be set to 1"]
141    #[inline(always)]
142    pub fn tx_fifo_mod_force_en(&mut self) -> TX_FIFO_MOD_FORCE_EN_W<FIFO_CONF_SPEC> {
143        TX_FIFO_MOD_FORCE_EN_W::new(self, 19)
144    }
145    #[doc = "Bit 20 - The bit should always be set to 1"]
146    #[inline(always)]
147    pub fn rx_fifo_mod_force_en(&mut self) -> RX_FIFO_MOD_FORCE_EN_W<FIFO_CONF_SPEC> {
148        RX_FIFO_MOD_FORCE_EN_W::new(self, 20)
149    }
150    #[doc = "Bit 21 - force write back rx data to memory"]
151    #[inline(always)]
152    pub fn rx_fifo_sync(&mut self) -> RX_FIFO_SYNC_W<FIFO_CONF_SPEC> {
153        RX_FIFO_SYNC_W::new(self, 21)
154    }
155    #[doc = "Bit 22 - Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
156    #[inline(always)]
157    pub fn rx_24msb_en(&mut self) -> RX_24MSB_EN_W<FIFO_CONF_SPEC> {
158        RX_24MSB_EN_W::new(self, 22)
159    }
160    #[doc = "Bit 23 - Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo"]
161    #[inline(always)]
162    pub fn tx_24msb_en(&mut self) -> TX_24MSB_EN_W<FIFO_CONF_SPEC> {
163        TX_24MSB_EN_W::new(self, 23)
164    }
165}
166#[doc = "I2S FIFO configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct FIFO_CONF_SPEC;
168impl crate::RegisterSpec for FIFO_CONF_SPEC {
169    type Ux = u32;
170}
171#[doc = "`read()` method returns [`fifo_conf::R`](R) reader structure"]
172impl crate::Readable for FIFO_CONF_SPEC {}
173#[doc = "`write(|w| ..)` method takes [`fifo_conf::W`](W) writer structure"]
174impl crate::Writable for FIFO_CONF_SPEC {
175    type Safety = crate::Unsafe;
176    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
177    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178}
179#[doc = "`reset()` method sets FIFO_CONF to value 0x1820"]
180impl crate::Resettable for FIFO_CONF_SPEC {
181    const RESET_VALUE: u32 = 0x1820;
182}
esp32s2/i2s0/fifo_conf.rs

esp32s2/i2s0/
fifo_conf.rs
