Expand description
UHCI configuration register
Structs§
- CONF1_
SPEC - UHCI configuration register
Type Aliases§
- CHECK_
OWNER_ R - Field
CHECK_OWNER
reader - 1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor. - CHECK_
OWNER_ W - Field
CHECK_OWNER
writer - 1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor. - CHECK_
SEQ_ EN_ R - Field
CHECK_SEQ_EN
reader - This is the enable bit to check sequence number when UHCI receives a data packet. - CHECK_
SEQ_ EN_ W - Field
CHECK_SEQ_EN
writer - This is the enable bit to check sequence number when UHCI receives a data packet. - CHECK_
SUM_ EN_ R - Field
CHECK_SUM_EN
reader - This is the enable bit to check header checksum when UHCI receives a data packet. - CHECK_
SUM_ EN_ W - Field
CHECK_SUM_EN
writer - This is the enable bit to check header checksum when UHCI receives a data packet. - CRC_
DISABLE_ R - Field
CRC_DISABLE
reader - Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1. - CRC_
DISABLE_ W - Field
CRC_DISABLE
writer - Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1. - DMA_
INFIFO_ FULL_ THRS_ R - Field
DMA_INFIFO_FULL_THRS
reader - This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register. - DMA_
INFIFO_ FULL_ THRS_ W - Field
DMA_INFIFO_FULL_THRS
writer - This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register. - R
- Register
CONF1
reader - SAVE_
HEAD_ R - Field
SAVE_HEAD
reader - Set this bit to save the packet header when UHCI receives a data packet. - SAVE_
HEAD_ W - Field
SAVE_HEAD
writer - Set this bit to save the packet header when UHCI receives a data packet. - SW_
START_ R - Field
SW_START
reader - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1. - SW_
START_ W - Field
SW_START
writer - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1. - TX_
ACK_ NUM_ RE_ R - Field
TX_ACK_NUM_RE
reader - Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit. - TX_
ACK_ NUM_ RE_ W - Field
TX_ACK_NUM_RE
writer - Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit. - TX_
CHECK_ SUM_ RE_ R - Field
TX_CHECK_SUM_RE
reader - Set this bit to encode the data packet with a checksum. - TX_
CHECK_ SUM_ RE_ W - Field
TX_CHECK_SUM_RE
writer - Set this bit to encode the data packet with a checksum. - W
- Register
CONF1
writer - WAIT_
SW_ START_ R - Field
WAIT_SW_START
reader - The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1. - WAIT_
SW_ START_ W - Field
WAIT_SW_START
writer - The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1.