Expand description
SPI USER control register
Structs§
- USER_
SPEC - SPI USER control register
Type Aliases§
- CK_
OUT_ EDGE_ R - Field
CK_OUT_EDGE
reader - the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state. - CK_
OUT_ EDGE_ W - Field
CK_OUT_EDGE
writer - the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state. - CS_
HOLD_ R - Field
CS_HOLD
reader - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. - CS_
HOLD_ W - Field
CS_HOLD
writer - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. - CS_
SETUP_ R - Field
CS_SETUP
reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. - CS_
SETUP_ W - Field
CS_SETUP
writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. - DOUTDIN_
R - Field
DOUTDIN
reader - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. - DOUTDIN_
W - Field
DOUTDIN
writer - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. - FWRITE_
DUAL_ R - Field
FWRITE_DUAL
reader - In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state. - FWRITE_
DUAL_ W - Field
FWRITE_DUAL
writer - In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state. - FWRITE_
OCT_ R - Field
FWRITE_OCT
reader - In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state. - FWRITE_
OCT_ W - Field
FWRITE_OCT
writer - In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state. - FWRITE_
QUAD_ R - Field
FWRITE_QUAD
reader - In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state. - FWRITE_
QUAD_ W - Field
FWRITE_QUAD
writer - In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state. - OPI_
MODE_ R - Field
OPI_MODE
reader - Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state. - OPI_
MODE_ W - Field
OPI_MODE
writer - Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state. - QPI_
MODE_ R - Field
QPI_MODE
reader - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. - QPI_
MODE_ W - Field
QPI_MODE
writer - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. - R
- Register
USER
reader - RD_
BYTE_ ORDER_ R - Field
RD_BYTE_ORDER
reader - In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state. - RD_
BYTE_ ORDER_ W - Field
RD_BYTE_ORDER
writer - In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state. - RSCK_
I_ EDGE_ R - Field
RSCK_I_EDGE
reader - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. - RSCK_
I_ EDGE_ W - Field
RSCK_I_EDGE
writer - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. - SIO_R
- Field
SIO
reader - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. - SIO_W
- Field
SIO
writer - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. - TSCK_
I_ EDGE_ R - Field
TSCK_I_EDGE
reader - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. - TSCK_
I_ EDGE_ W - Field
TSCK_I_EDGE
writer - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. - USR_
ADDR_ HOLD_ R - Field
USR_ADDR_HOLD
reader - spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
ADDR_ HOLD_ W - Field
USR_ADDR_HOLD
writer - spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
ADDR_ R - Field
USR_ADDR
reader - This bit enable the address phase of an operation. Can be configured in CONF state. - USR_
ADDR_ W - Field
USR_ADDR
writer - This bit enable the address phase of an operation. Can be configured in CONF state. - USR_
CMD_ HOLD_ R - Field
USR_CMD_HOLD
reader - spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
CMD_ HOLD_ W - Field
USR_CMD_HOLD
writer - spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
COMMAND_ R - Field
USR_COMMAND
reader - This bit enable the command phase of an operation. Can be configured in CONF state. - USR_
COMMAND_ W - Field
USR_COMMAND
writer - This bit enable the command phase of an operation. Can be configured in CONF state. - USR_
CONF_ NXT_ R - Field
USR_CONF_NXT
reader - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. - USR_
CONF_ NXT_ W - Field
USR_CONF_NXT
writer - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. - USR_
DIN_ HOLD_ R - Field
USR_DIN_HOLD
reader - spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
DIN_ HOLD_ W - Field
USR_DIN_HOLD
writer - spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
DOUT_ HOLD_ R - Field
USR_DOUT_HOLD
reader - spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
DOUT_ HOLD_ W - Field
USR_DOUT_HOLD
writer - spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
DUMMY_ HOLD_ R - Field
USR_DUMMY_HOLD
reader - spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
DUMMY_ HOLD_ W - Field
USR_DUMMY_HOLD
writer - spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
DUMMY_ IDLE_ R - Field
USR_DUMMY_IDLE
reader - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. - USR_
DUMMY_ IDLE_ W - Field
USR_DUMMY_IDLE
writer - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. - USR_
DUMMY_ R - Field
USR_DUMMY
reader - This bit enable the dummy phase of an operation. Can be configured in CONF state. - USR_
DUMMY_ W - Field
USR_DUMMY
writer - This bit enable the dummy phase of an operation. Can be configured in CONF state. - USR_
HOLD_ POL_ R - Field
USR_HOLD_POL
reader - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state. - USR_
HOLD_ POL_ W - Field
USR_HOLD_POL
writer - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state. - USR_
MISO_ HIGHPART_ R - Field
USR_MISO_HIGHPART
reader - read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state. - USR_
MISO_ HIGHPART_ W - Field
USR_MISO_HIGHPART
writer - read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state. - USR_
MISO_ R - Field
USR_MISO
reader - This bit enable the read-data phase of an operation. Can be configured in CONF state. - USR_
MISO_ W - Field
USR_MISO
writer - This bit enable the read-data phase of an operation. Can be configured in CONF state. - USR_
MOSI_ HIGHPART_ R - Field
USR_MOSI_HIGHPART
reader - write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state. - USR_
MOSI_ HIGHPART_ W - Field
USR_MOSI_HIGHPART
writer - write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state. - USR_
MOSI_ R - Field
USR_MOSI
reader - This bit enable the write-data phase of an operation. Can be configured in CONF state. - USR_
MOSI_ W - Field
USR_MOSI
writer - This bit enable the write-data phase of an operation. Can be configured in CONF state. - USR_
PREP_ HOLD_ R - Field
USR_PREP_HOLD
reader - spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - USR_
PREP_ HOLD_ W - Field
USR_PREP_HOLD
writer - spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. - W
- Register
USER
writer - WR_
BYTE_ ORDER_ R - Field
WR_BYTE_ORDER
reader - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state. - WR_
BYTE_ ORDER_ W - Field
WR_BYTE_ORDER
writer - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state.