Module sram_dwr_cmd

Source
Expand description

SPI Memory SRAM DWR CMD Register

Structs§

SRAM_DWR_CMD_SPEC
SPI Memory SRAM DWR CMD Register

Type Aliases§

CACHE_SRAM_USR_WR_CMD_BITLEN_R
Field CACHE_SRAM_USR_WR_CMD_BITLEN reader - For SPI0, when cache mode is enabled, it is the length in bits of the command phase for SRAM. The register value shall be (bit_num-1).
CACHE_SRAM_USR_WR_CMD_BITLEN_W
Field CACHE_SRAM_USR_WR_CMD_BITLEN writer - For SPI0, when cache mode is enabled, it is the length in bits of the command phase for SRAM. The register value shall be (bit_num-1).
CACHE_SRAM_USR_WR_CMD_VALUE_R
Field CACHE_SRAM_USR_WR_CMD_VALUE reader - For SPI0, when cache mode is enabled, it is the write command value of the command phase for SRAM.
CACHE_SRAM_USR_WR_CMD_VALUE_W
Field CACHE_SRAM_USR_WR_CMD_VALUE writer - For SPI0, when cache mode is enabled, it is the write command value of the command phase for SRAM.
R
Register SRAM_DWR_CMD reader
W
Register SRAM_DWR_CMD writer