Expand description
SPI Memory SRAM DWR CMD Register
Structs§
- SRAM_
DWR_ CMD_ SPEC - SPI Memory SRAM DWR CMD Register
Type Aliases§
- CACHE_
SRAM_ USR_ WR_ CMD_ BITLEN_ R - Field
CACHE_SRAM_USR_WR_CMD_BITLEN
reader - For SPI0, when cache mode is enabled, it is the length in bits of the command phase for SRAM. The register value shall be (bit_num-1). - CACHE_
SRAM_ USR_ WR_ CMD_ BITLEN_ W - Field
CACHE_SRAM_USR_WR_CMD_BITLEN
writer - For SPI0, when cache mode is enabled, it is the length in bits of the command phase for SRAM. The register value shall be (bit_num-1). - CACHE_
SRAM_ USR_ WR_ CMD_ VALUE_ R - Field
CACHE_SRAM_USR_WR_CMD_VALUE
reader - For SPI0, when cache mode is enabled, it is the write command value of the command phase for SRAM. - CACHE_
SRAM_ USR_ WR_ CMD_ VALUE_ W - Field
CACHE_SRAM_USR_WR_CMD_VALUE
writer - For SPI0, when cache mode is enabled, it is the write command value of the command phase for SRAM. - R
- Register
SRAM_DWR_CMD
reader - W
- Register
SRAM_DWR_CMD
writer