Module ctrl2

SPI control register 2

Structs

CTRL2_SPEC

SPI control register 2

Type Aliases

CS_DELAY_MODE_R

Field CS_DELAY_MODE reader - spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state.

CS_DELAY_MODE_W

Field CS_DELAY_MODE writer - spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state.

CS_DELAY_NUM_R

Field CS_DELAY_NUM reader - spi_cs signal is delayed by system clock cycles. Can be configured in CONF state.

CS_DELAY_NUM_W

Field CS_DELAY_NUM writer - spi_cs signal is delayed by system clock cycles. Can be configured in CONF state.

CS_HOLD_TIME_R

Field CS_HOLD_TIME reader - delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state.

CS_HOLD_TIME_W

Field CS_HOLD_TIME writer - delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state.

CS_SETUP_TIME_R

Field CS_SETUP_TIME reader - (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state.

CS_SETUP_TIME_W

Field CS_SETUP_TIME writer - (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state.

R

Register CTRL2 reader

W

Register CTRL2 writer